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Showing items 46-55 of 347  (35 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2020-04-16T02:35:13Z Image Shading Taking into Account Relativistic Effects Chang, M.-C.; Lai, F.; Chen, W.-C.; FEI-PEI LAI
臺大學術典藏 2020-04-16T02:35:13Z Intelligent code migration technique for synchronisation operations on a multiprocessor Hwang, R.-Y.;Lai, F.; Hwang, R.-Y.; Lai, F.; FEI-PEI LAI
臺大學術典藏 2020-04-16T02:35:13Z Guiding instruction scheduling with synchronization markers on a superscalar based multiprocessor Hwang, R.-Y.; Lai, F.; FEI-PEI LAI
臺大學術典藏 2020-04-16T02:35:12Z Performance analysis of broadcast in mobile ad hoc networks with synchronized and non-synchronized reception Pan, K.-H.; Wu, H.-K.; Shang, R.-J.; Lai, F.; FEI-PEI LAI
臺大學術典藏 2020-04-16T02:35:12Z Requirements specification and analysis of digital systems using fuzzy and marked Petri nets Shen, V.R.L.; Lai, F.; FEI-PEI LAI
臺大學術典藏 2020-04-16T02:35:12Z Region-based template deformation and masking for eye-feature extraction and description Deng, J.-Y.; Lai, F.; FEI-PEI LAI
臺大學術典藏 2020-04-16T02:35:12Z Hybrid parallel circuit simulation approaches Naroska, E.; Shang, R.-J.; Lai, F.; Schwiegelshohn, U.; FEI-PEI LAI
臺大學術典藏 2020-04-16T02:35:12Z Messagfer om the organizers FEI-PEI LAI; Hsu, C.-C.; Horiguchi, S.; Chang, J-F.; Maggs, B.; Lai, F.; Hsu, D.F.; Wu, J.S.
臺大學術典藏 2020-04-16T02:35:11Z Zero-aware asymmetric SRAM cell for reducing cache power in writing zero Chang, Y.-J.; Lai, F.; Yang, C.-L.; FEI-PEI LAI
臺大學術典藏 2020-04-16T02:35:11Z Power analysis of bipartition and dual-encoding architecture for pipelined circuits Ho, C.-L.; Lai, F.; FEI-PEI LAI; Naroska, E.; Ruan, S.-J.

Showing items 46-55 of 347  (35 Page(s) Totally)
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