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Showing items 101-150 of 190  (4 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 1990-03 A New Method for Two-Dimensional VLSI Layout Compaction Design Chen, H. F.; Hsiao, P, Y.; Feng, Wu-Shiung; Chen, Sao-Jie; Chen, H. F.; Hsiao, P, Y.; 馮武雄; 陳少傑; Feng, Wu-Shiung; Chen, Sao-Jie
臺大學術典藏 1990-03 An Alternating Router for Compacted Routing Area Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung; Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung
臺大學術典藏 1990-03 Routing Techniques in Staircase Channels Fang, S. C.; Chen, Sao-Jie; Feng, Wu-Shiung; Fang, S. C.; 陳少傑; 馮武雄; Fang, S. C.; Chen, Sao-Jie; Feng, Wu-Shiung
國立臺灣大學 1990 A Topological Sorting Algorithm for Three-Layer Channel Routing Chang, K. E.; Lai, T. H.; 馮武雄; Chang, K. E.; Lai, T. H.; Feng, Wu-Shiung
國立臺灣大學 1990 An Application of an Expert System in Layout Compaction of VlSI Design Hsiao, P. Y.; 馮武雄; Chen, H. F.; Hsiao, P. Y.; Feng, Wu-Shiung; Chen, H. F.
國立臺灣大學 1990 Generalized Terminal Connectivity Problem Tsai, C. C.; Chen, S. J.; 馮武雄; Tsai, C. C.; Chen, S. J.; Feng, Wu-Shiung
國立臺灣大學 1990 New Algorithms Based on Multiple Storage Quadtrees in Hierarchical Compaction of VlSI Mask Layout Hsiao, P. Y.; 馮武雄; Chen, H. F.; Hsiao, P. Y.; Feng, Wu-Shiung; Chen, H. F.
國立臺灣大學 1990 Using Multiple Storage Quad Tree on a Hierarchical VLSI Compaction Scheme Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學 1990 An Improved Analytical Model of Short Channel MOSFETs Suitable for Circuit Simulation Chow, H. C.; Wang, J. H.; Kuo, J, B.; 馮武雄; Chow, H. C.; Wang, J. H.; Kuo, J, B.; Feng, Wu-Shiung
國立臺灣大學 1990 Optimal Aspect Ratios of Building Blocks for Floorplan Designs Shih, P. H.; 馮武雄; Shih, P. H.; Feng, Wu-Shiung
國立臺灣大學 1990 Optimal Aspect Ratios of Building Blocks for Generally Structured VLSI Floorplan Design Shih, P. H.; 馮武雄; Shih, P. H.; Feng, Wu-Shiung
國立臺灣大學 1990 Via Minimization with Associated Constraints in Three-Layer Routing Problem Fang, S. C.; Chang, K. E.; 馮武雄; Fang, S. C.; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學 1990 Generalized terminal connectivity problem for multilayer layout scheme Tsai, Chia-Chun; Chen, Sao-Jie; Feng, Wu-Shiung
國立臺灣大學 1989-12 An H-V Tile-Expansion Router Tsai, C. C.; 陳少傑; 馮武雄; Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung
臺大學術典藏 1989-12 An H-V Tile-Expansion Router Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung; Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung
國立臺灣大學 1989-08 The Control Model for a Knowledge-Based Approach to VLSI Compaction Design Chen, S. F. Steven; Hsiao, P. Y.; 馮武雄; Wang, W. T.; Dai, S. N.; Chen, S. F. Steven; Hsiao, P. Y.; Feng, Wu-Shiung; Wang, W. T.; Dai, S. N.
國立臺灣大學 1989-06 An Improved Control Strategy for Expert Compaction Design Hsiao, P. Y.; Chen, H. F.; 馮武雄; Chen, S. J.; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, S. J.; Tsai, C. C.
國立臺灣大學 1989-06 An Improved Control Strategy for Expert Layout Compaction Design Hsiao, P. Y.; Chen, H. F.; 馮武雄; 陳少傑; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.
臺大學術典藏 1989-06 An Improved Control Strategy for Expert Layout Compaction Design Chen, H. F.; 馮武雄; 陳少傑; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.; Hsiao, P. Y.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.
國立臺灣大學 1989 A Novel Implementation of Pipelined Toeplitz System Solver Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung
國立臺灣大學 1989 Constrained Via Minimization for Three-Layer Routing Chang, K. E.; Jyu, H. F.; 馮武雄; Chang, K. E.; Jyu, H. F.; Feng, Wu-Shiung
國立臺灣大學 1989 Graph Contractibility Problem for VLSI Layer Assignment Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學 1989 Using Hierarchical Multiple Storage Quad Tree on a Constraint-Graph Layout Compaction Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學 1989 A Heuristic Scanning Line Approach for an Expert Layout Compactor Hsiao, P. Y.; Chen, S. F. Steven; 馮武雄; Hsiao, P. Y.; Chen, S. F. Steven; Feng, Wu-Shiung
國立臺灣大學 1989 An Efficient Layer Assignment for Three-Layer Restrictive VLSI Routing Chang, K. E.; Fang, S. C.; 馮武雄; Chang, K. E.; Fang, S. C.; Feng, Wu-Shiung
國立臺灣大學 1989 Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme Tsai, C. C.; 馮武雄; 陳少傑; Hsiao, P, Y.; Chen, H. F.; Tsai, C. C.; Feng, Wu-Shiung; Chen, Sao-Jie; Hsiao, P, Y.; Chen, H. F.
國立臺灣大學 1989 The Pin Alignment in VLSI Routing with Movable Terminals Chang, K. E.; Fu, C. M.; 馮武雄; Chang, K. E.; Fu, C. M.; Feng, Wu-Shiung
臺大學術典藏 1989 Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme Tsai, C. C.; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.; 馮武雄; 陳少傑; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Chen, H. F.
國立臺灣大學 1988-12 An Incremental Design Rule Checking Based on Quad Tree Representations Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學 1988-10 A rule-based compactor for VLSI/CAD mask layout Hsiao, Pei-Yung; Chen, Yung Syau; Feng, Wu-Shiung; Parng, T.M.; Hsu, C.C.
國立臺灣大學 1988-06 An edge-oriented compaction scheme based on multiple storage quad tree Hsiao, Pei-Yung; Feng, Wu-Shiung
國立臺灣大學 1988 A Global Approach for Via Minimization Jyu, H. F.; 馮武雄; Jyu, H. F.; Feng, Wu-Shiung
國立臺灣大學 1988 A Rule-Based Compactor for VLSI/CAD Mask Layout Hsiao, P. Y.; Syau, C. Y.; 馮武雄; 龐台銘; Hsu, C. C.; Hsiao, P. Y.; Syau, C. Y.; Feng, Wu-Shiung; Parng, Tai-Ming; Hsu, C. C.
國立臺灣大學 1988 A Rule-Based Expert System for VLSI Layout Compaction Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學 1988 An Edge-Oriented Compaction Scheme Based on Multiple Storage Quad Tree Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學 1988 The Topological Order Determination for Three-Layer Channel Routing Problem Chang, K. E.; Lai, T. H.; 馮武雄; Chang, K. E.; Lai, T. H.; Feng, Wu-Shiung
國立臺灣大學 1987-12 A New Dynamic Switch-Box Router Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學 1987-09 A Fault Grader Chen, T. H.; 馮武雄; 林呈祥; Chen, T. H.; Feng, Wu-Shiung; Lin, Chen-Shang
國立臺灣大學 1987-09 Automatic Floorplan and Placement for Hierarchical Layout System Chen, J. Y.; 馮武雄; Chen, J. Y.; Feng, Wu-Shiung
國立臺灣大學 1987-09 FAMI:A Fast Logic Minimizer for PLA Design Maa, N. S.; 馮武雄; Maa, N. S.; Feng, Wu-Shiung
國立臺灣大學 1987-05 Hierarchical Layout System Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; 馮武雄; Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; Feng, Wu-Shiung
國立臺灣大學 1987-05 Multi-Level Hierarchical Function Simulation 馮武雄; Lee, K. S.; Tu, H.; Feng, Wu-Shiung; Lee, K. S.; Tu, H.
國立臺灣大學 1987-05 The Multiple Storage Quad-Tree in Constraint-Graph Compaction of VLSI Layout Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學 1987 Extraction and Modeling of VLSI Cell Layout Yeh, K. F.; 馮武雄; Yeh, K. F.; Feng, Wu-Shiung
國立臺灣大學 1987 HILAS-Hierarchical Interactive Layout System Tsai, C. C.; 馮武雄; Tsai, C. C.; Feng, Wu-Shiung
國立臺灣大學 1987 Placement and Routing with Power/Ground Chen, J. Y.; Wang, C. S.; Tseng, J. N.; 馮武雄; Chen, J. Y.; Wang, C. S.; Tseng, J. N.; Feng, Wu-Shiung
國立臺灣大學 1987 Two-Layer Corner-Stitching for Interactive Routing and Pushing of Schematic Editor Kuop, S. T.; 馮武雄; Kuop, S. T.; Feng, Wu-Shiung
國立臺灣大學 1987 With Multiple Storage Quad Tree on the Constraint Graph Compaction of the VLSI Large-Cell Lay-Out-Editor Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學 1986-10 MOSFET Drain Breakdown Voltage 馮武雄; Chan, T. Y.; Hu, C.; Feng, Wu-Shiung; Chan, T. Y.; Hu, C.
國立臺灣大學 1986-09 Design and Implementation of Microprogrammed-Controller Synthesizer 于惠中; Parng, T. P.; 馮武雄; Chen, C. F.; Sun, L. F.; Yu, Hui-Jung; Parng, T. P.; Feng, Wu-Shiung; Chen, C. F.; Sun, L. F.

Showing items 101-150 of 190  (4 Page(s) Totally)
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