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Taiwan Academic Institutional Repository >
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"feng wu shiung"
Showing items 141-150 of 190 (19 Page(s) Totally)
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| 國立臺灣大學 |
1987-05 |
Hierarchical Layout System
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Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; 馮武雄; Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1987-05 |
Multi-Level Hierarchical Function Simulation
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馮武雄; Lee, K. S.; Tu, H.; Feng, Wu-Shiung; Lee, K. S.; Tu, H. |
| 國立臺灣大學 |
1987-05 |
The Multiple Storage Quad-Tree in Constraint-Graph Compaction of VLSI Layout
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Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1987 |
Extraction and Modeling of VLSI Cell Layout
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Yeh, K. F.; 馮武雄; Yeh, K. F.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1987 |
HILAS-Hierarchical Interactive Layout System
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Tsai, C. C.; 馮武雄; Tsai, C. C.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1987 |
Placement and Routing with Power/Ground
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Chen, J. Y.; Wang, C. S.; Tseng, J. N.; 馮武雄; Chen, J. Y.; Wang, C. S.; Tseng, J. N.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1987 |
Two-Layer Corner-Stitching for Interactive Routing and Pushing of Schematic Editor
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Kuop, S. T.; 馮武雄; Kuop, S. T.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1987 |
With Multiple Storage Quad Tree on the Constraint Graph Compaction of the VLSI Large-Cell Lay-Out-Editor
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Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-10 |
MOSFET Drain Breakdown Voltage
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馮武雄; Chan, T. Y.; Hu, C.; Feng, Wu-Shiung; Chan, T. Y.; Hu, C. |
| 國立臺灣大學 |
1986-09 |
Design and Implementation of Microprogrammed-Controller Synthesizer
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于惠中; Parng, T. P.; 馮武雄; Chen, C. F.; Sun, L. F.; Yu, Hui-Jung; Parng, T. P.; Feng, Wu-Shiung; Chen, C. F.; Sun, L. F. |
Showing items 141-150 of 190 (19 Page(s) Totally)
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