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Taiwan Academic Institutional Repository >
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"feng wu shiung"
Showing items 161-170 of 190 (19 Page(s) Totally)
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| 國立臺灣大學 |
1986-08 |
Hierarchical Timing Verification System for Multiple Clocked Logic Circuit
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Tyan, C. Y.; 馮武雄; 于惠中; Yeh, T. S.; Tyan, C. Y.; Feng, Wu-Shiung; Yu, Hui-Jung; Yeh, T. S. |
| 國立臺灣大學 |
1986-08 |
Integrated VLSI Design System:Design Entry System
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馮武雄; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-08 |
Integrated VlSI Design System:Layout System
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馮武雄; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-08 |
LED - A Net-List Driven Layout Editor
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Jan, S. S.; Tsai, C. C.; 馮武雄; Jan, S. S.; Tsai, C. C.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-08 |
Schematic Layout Editor
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Wang, C. I.; 馮武雄; 龐台銘; Wang, C. I.; Feng, Wu-Shiung; Parng, Tai-Ming |
| 國立臺灣大學 |
1986-08 |
Test Sequence Generator
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Ou, H. C.; 馮武雄; Liaw, H. T.; Ou, H. C.; Feng, Wu-Shiung; Liaw, H. T. |
| 國立臺灣大學 |
1986-08 |
Top-Down Placement for Hierarchical Layout System
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Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-05 |
Lattice Filter Array Implementation of Pipelined Toeplitz System Solver
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Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986 |
An Interactive Symbolic Layout System for Integrated-Circuit Design - HISLID
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馮武雄; 于惠中; Feng, Wu-Shiung; Yu, Hui-Jung |
| 國立臺灣大學 |
1986 |
Parallel Algorithm and Architecture for Solving Covariance Eigen System
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Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Jou, I. C.; Hu, Y. H.; Yu, Hui-Jung; Feng, Wu-Shiung |
Showing items 161-170 of 190 (19 Page(s) Totally)
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