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"feng wu shiung"的相關文件
顯示項目 146-170 / 190 (共8頁)
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| 國立臺灣大學 |
1987 |
Placement and Routing with Power/Ground
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Chen, J. Y.; Wang, C. S.; Tseng, J. N.; 馮武雄; Chen, J. Y.; Wang, C. S.; Tseng, J. N.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1987 |
Two-Layer Corner-Stitching for Interactive Routing and Pushing of Schematic Editor
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Kuop, S. T.; 馮武雄; Kuop, S. T.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1987 |
With Multiple Storage Quad Tree on the Constraint Graph Compaction of the VLSI Large-Cell Lay-Out-Editor
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Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-10 |
MOSFET Drain Breakdown Voltage
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馮武雄; Chan, T. Y.; Hu, C.; Feng, Wu-Shiung; Chan, T. Y.; Hu, C. |
| 國立臺灣大學 |
1986-09 |
Design and Implementation of Microprogrammed-Controller Synthesizer
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于惠中; Parng, T. P.; 馮武雄; Chen, C. F.; Sun, L. F.; Yu, Hui-Jung; Parng, T. P.; Feng, Wu-Shiung; Chen, C. F.; Sun, L. F. |
| 國立臺灣大學 |
1986-09 |
Design and Implementation of Schematic-Entry Generation System
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-09 |
Hierarchical Placement System for VLSI Design
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-09 |
HILAS-an Hierarchical and Interactive Layout Editor System
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-09 |
Integrated Entry and Verification System for VLSI Design
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-09 |
Integrated VLSI Design System - Main System Design
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Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D. |
| 國立臺灣大學 |
1986-09 |
Layout System Vol. 4:an Automatic Placement System for VLSI Layouts
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Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-09 |
Multiple-Level Abstraction for Hierarchical VLSI Storage System
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Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D. |
| 國立臺灣大學 |
1986-09 |
Netlist-Driven Cell-Layout Editor System
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-09 |
Private Database Management System for VLSI Design
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Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D. |
| 國立臺灣大學 |
1986-09 |
Three Layer Routing Algorithms for VLSI Design
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-08 |
Hierarchical Timing Verification System for Multiple Clocked Logic Circuit
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Tyan, C. Y.; 馮武雄; 于惠中; Yeh, T. S.; Tyan, C. Y.; Feng, Wu-Shiung; Yu, Hui-Jung; Yeh, T. S. |
| 國立臺灣大學 |
1986-08 |
Integrated VLSI Design System:Design Entry System
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馮武雄; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-08 |
Integrated VlSI Design System:Layout System
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馮武雄; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-08 |
LED - A Net-List Driven Layout Editor
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Jan, S. S.; Tsai, C. C.; 馮武雄; Jan, S. S.; Tsai, C. C.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-08 |
Schematic Layout Editor
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Wang, C. I.; 馮武雄; 龐台銘; Wang, C. I.; Feng, Wu-Shiung; Parng, Tai-Ming |
| 國立臺灣大學 |
1986-08 |
Test Sequence Generator
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Ou, H. C.; 馮武雄; Liaw, H. T.; Ou, H. C.; Feng, Wu-Shiung; Liaw, H. T. |
| 國立臺灣大學 |
1986-08 |
Top-Down Placement for Hierarchical Layout System
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Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-05 |
Lattice Filter Array Implementation of Pipelined Toeplitz System Solver
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Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986 |
An Interactive Symbolic Layout System for Integrated-Circuit Design - HISLID
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馮武雄; 于惠中; Feng, Wu-Shiung; Yu, Hui-Jung |
| 國立臺灣大學 |
1986 |
Parallel Algorithm and Architecture for Solving Covariance Eigen System
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Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Jou, I. C.; Hu, Y. H.; Yu, Hui-Jung; Feng, Wu-Shiung |
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