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Institution	Date	Title	Author
國立臺灣大學	1990	Optimal Aspect Ratios of Building Blocks for Generally Structured VLSI Floorplan Design	Shih, P. H.; 馮武雄; Shih, P. H.; Feng, Wu-Shiung
國立臺灣大學	1990	Via Minimization with Associated Constraints in Three-Layer Routing Problem	Fang, S. C.; Chang, K. E.; 馮武雄; Fang, S. C.; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學	1990	Generalized terminal connectivity problem for multilayer layout scheme	Tsai, Chia-Chun; Chen, Sao-Jie; Feng, Wu-Shiung
國立臺灣大學	1989-12	An H-V Tile-Expansion Router	Tsai, C. C.; 陳少傑; 馮武雄; Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung
臺大學術典藏	1989-12	An H-V Tile-Expansion Router	Tsai, C. C.; Chen, Sao-Jie; Feng, Wu-Shiung; Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung
國立臺灣大學	1989-08	The Control Model for a Knowledge-Based Approach to VLSI Compaction Design	Chen, S. F. Steven; Hsiao, P. Y.; 馮武雄; Wang, W. T.; Dai, S. N.; Chen, S. F. Steven; Hsiao, P. Y.; Feng, Wu-Shiung; Wang, W. T.; Dai, S. N.
國立臺灣大學	1989-06	An Improved Control Strategy for Expert Compaction Design	Hsiao, P. Y.; Chen, H. F.; 馮武雄; Chen, S. J.; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, S. J.; Tsai, C. C.
國立臺灣大學	1989-06	An Improved Control Strategy for Expert Layout Compaction Design	Hsiao, P. Y.; Chen, H. F.; 馮武雄; 陳少傑; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.
臺大學術典藏	1989-06	An Improved Control Strategy for Expert Layout Compaction Design	Chen, H. F.; 馮武雄; 陳少傑; Tsai, C. C.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.; Hsiao, P. Y.; Hsiao, P. Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.
國立臺灣大學	1989	A Novel Implementation of Pipelined Toeplitz System Solver	Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung
國立臺灣大學	1989	Constrained Via Minimization for Three-Layer Routing	Chang, K. E.; Jyu, H. F.; 馮武雄; Chang, K. E.; Jyu, H. F.; Feng, Wu-Shiung
國立臺灣大學	1989	Graph Contractibility Problem for VLSI Layer Assignment	Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學	1989	Using Hierarchical Multiple Storage Quad Tree on a Constraint-Graph Layout Compaction	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1989	A Heuristic Scanning Line Approach for an Expert Layout Compactor	Hsiao, P. Y.; Chen, S. F. Steven; 馮武雄; Hsiao, P. Y.; Chen, S. F. Steven; Feng, Wu-Shiung
國立臺灣大學	1989	An Efficient Layer Assignment for Three-Layer Restrictive VLSI Routing	Chang, K. E.; Fang, S. C.; 馮武雄; Chang, K. E.; Fang, S. C.; Feng, Wu-Shiung
國立臺灣大學	1989	Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme	Tsai, C. C.; 馮武雄; 陳少傑; Hsiao, P, Y.; Chen, H. F.; Tsai, C. C.; Feng, Wu-Shiung; Chen, Sao-Jie; Hsiao, P, Y.; Chen, H. F.
國立臺灣大學	1989	The Pin Alignment in VLSI Routing with Movable Terminals	Chang, K. E.; Fu, C. M.; 馮武雄; Chang, K. E.; Fu, C. M.; Feng, Wu-Shiung
臺大學術典藏	1989	Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme	Tsai, C. C.; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.; 馮武雄; 陳少傑; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Chen, H. F.
國立臺灣大學	1988-12	An Incremental Design Rule Checking Based on Quad Tree Representations	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1988-10	A rule-based compactor for VLSI/CAD mask layout	Hsiao, Pei-Yung; Chen, Yung Syau; Feng, Wu-Shiung; Parng, T.M.; Hsu, C.C.
國立臺灣大學	1988-06	An edge-oriented compaction scheme based on multiple storage quad tree	Hsiao, Pei-Yung; Feng, Wu-Shiung
國立臺灣大學	1988	A Global Approach for Via Minimization	Jyu, H. F.; 馮武雄; Jyu, H. F.; Feng, Wu-Shiung
國立臺灣大學	1988	A Rule-Based Compactor for VLSI/CAD Mask Layout	Hsiao, P. Y.; Syau, C. Y.; 馮武雄; 龐台銘; Hsu, C. C.; Hsiao, P. Y.; Syau, C. Y.; Feng, Wu-Shiung; Parng, Tai-Ming; Hsu, C. C.
國立臺灣大學	1988	A Rule-Based Expert System for VLSI Layout Compaction	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1988	An Edge-Oriented Compaction Scheme Based on Multiple Storage Quad Tree	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung

Showing items 111-135 of 190 (8 Page(s) Totally)
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