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Institution	Date	Title	Author
國立臺灣大學	1989	Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme	Tsai, C. C.; 馮武雄; 陳少傑; Hsiao, P, Y.; Chen, H. F.; Tsai, C. C.; Feng, Wu-Shiung; Chen, Sao-Jie; Hsiao, P, Y.; Chen, H. F.
國立臺灣大學	1989	The Pin Alignment in VLSI Routing with Movable Terminals	Chang, K. E.; Fu, C. M.; 馮武雄; Chang, K. E.; Fu, C. M.; Feng, Wu-Shiung
臺大學術典藏	1989	Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme	Tsai, C. C.; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.; 馮武雄; 陳少傑; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Chen, H. F.
國立臺灣大學	1988-12	An Incremental Design Rule Checking Based on Quad Tree Representations	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1988-10	A rule-based compactor for VLSI/CAD mask layout	Hsiao, Pei-Yung; Chen, Yung Syau; Feng, Wu-Shiung; Parng, T.M.; Hsu, C.C.
國立臺灣大學	1988-06	An edge-oriented compaction scheme based on multiple storage quad tree	Hsiao, Pei-Yung; Feng, Wu-Shiung
國立臺灣大學	1988	A Global Approach for Via Minimization	Jyu, H. F.; 馮武雄; Jyu, H. F.; Feng, Wu-Shiung
國立臺灣大學	1988	A Rule-Based Compactor for VLSI/CAD Mask Layout	Hsiao, P. Y.; Syau, C. Y.; 馮武雄; 龐台銘; Hsu, C. C.; Hsiao, P. Y.; Syau, C. Y.; Feng, Wu-Shiung; Parng, Tai-Ming; Hsu, C. C.
國立臺灣大學	1988	A Rule-Based Expert System for VLSI Layout Compaction	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1988	An Edge-Oriented Compaction Scheme Based on Multiple Storage Quad Tree	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1988	The Topological Order Determination for Three-Layer Channel Routing Problem	Chang, K. E.; Lai, T. H.; 馮武雄; Chang, K. E.; Lai, T. H.; Feng, Wu-Shiung
國立臺灣大學	1987-12	A New Dynamic Switch-Box Router	Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學	1987-09	A Fault Grader	Chen, T. H.; 馮武雄; 林呈祥; Chen, T. H.; Feng, Wu-Shiung; Lin, Chen-Shang
國立臺灣大學	1987-09	Automatic Floorplan and Placement for Hierarchical Layout System	Chen, J. Y.; 馮武雄; Chen, J. Y.; Feng, Wu-Shiung
國立臺灣大學	1987-09	FAMI:A Fast Logic Minimizer for PLA Design	Maa, N. S.; 馮武雄; Maa, N. S.; Feng, Wu-Shiung
國立臺灣大學	1987-05	Hierarchical Layout System	Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; 馮武雄; Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; Feng, Wu-Shiung
國立臺灣大學	1987-05	Multi-Level Hierarchical Function Simulation	馮武雄; Lee, K. S.; Tu, H.; Feng, Wu-Shiung; Lee, K. S.; Tu, H.
國立臺灣大學	1987-05	The Multiple Storage Quad-Tree in Constraint-Graph Compaction of VLSI Layout	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1987	Extraction and Modeling of VLSI Cell Layout	Yeh, K. F.; 馮武雄; Yeh, K. F.; Feng, Wu-Shiung
國立臺灣大學	1987	HILAS-Hierarchical Interactive Layout System	Tsai, C. C.; 馮武雄; Tsai, C. C.; Feng, Wu-Shiung
國立臺灣大學	1987	Placement and Routing with Power/Ground	Chen, J. Y.; Wang, C. S.; Tseng, J. N.; 馮武雄; Chen, J. Y.; Wang, C. S.; Tseng, J. N.; Feng, Wu-Shiung
國立臺灣大學	1987	Two-Layer Corner-Stitching for Interactive Routing and Pushing of Schematic Editor	Kuop, S. T.; 馮武雄; Kuop, S. T.; Feng, Wu-Shiung
國立臺灣大學	1987	With Multiple Storage Quad Tree on the Constraint Graph Compaction of the VLSI Large-Cell Lay-Out-Editor	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1986-10	MOSFET Drain Breakdown Voltage	馮武雄; Chan, T. Y.; Hu, C.; Feng, Wu-Shiung; Chan, T. Y.; Hu, C.
國立臺灣大學	1986-09	Design and Implementation of Microprogrammed-Controller Synthesizer	于惠中; Parng, T. P.; 馮武雄; Chen, C. F.; Sun, L. F.; Yu, Hui-Jung; Parng, T. P.; Feng, Wu-Shiung; Chen, C. F.; Sun, L. F.
國立臺灣大學	1986-09	Design and Implementation of Schematic-Entry Generation System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Hierarchical Placement System for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	HILAS-an Hierarchical and Interactive Layout Editor System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Integrated Entry and Verification System for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Integrated VLSI Design System - Main System Design	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Layout System Vol. 4:an Automatic Placement System for VLSI Layouts	Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學	1986-09	Multiple-Level Abstraction for Hierarchical VLSI Storage System	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Netlist-Driven Cell-Layout Editor System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Private Database Management System for VLSI Design	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Three Layer Routing Algorithms for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-08	Hierarchical Timing Verification System for Multiple Clocked Logic Circuit	Tyan, C. Y.; 馮武雄; 于惠中; Yeh, T. S.; Tyan, C. Y.; Feng, Wu-Shiung; Yu, Hui-Jung; Yeh, T. S.
國立臺灣大學	1986-08	Integrated VLSI Design System:Design Entry System	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1986-08	Integrated VlSI Design System:Layout System	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1986-08	LED - A Net-List Driven Layout Editor	Jan, S. S.; Tsai, C. C.; 馮武雄; Jan, S. S.; Tsai, C. C.; Feng, Wu-Shiung
國立臺灣大學	1986-08	Schematic Layout Editor	Wang, C. I.; 馮武雄; 龐台銘; Wang, C. I.; Feng, Wu-Shiung; Parng, Tai-Ming
國立臺灣大學	1986-08	Test Sequence Generator	Ou, H. C.; 馮武雄; Liaw, H. T.; Ou, H. C.; Feng, Wu-Shiung; Liaw, H. T.
國立臺灣大學	1986-08	Top-Down Placement for Hierarchical Layout System	Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學	1986-05	Lattice Filter Array Implementation of Pipelined Toeplitz System Solver	Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung
國立臺灣大學	1986	An Interactive Symbolic Layout System for Integrated-Circuit Design - HISLID	馮武雄; 于惠中; Feng, Wu-Shiung; Yu, Hui-Jung
國立臺灣大學	1986	Parallel Algorithm and Architecture for Solving Covariance Eigen System	Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Jou, I. C.; Hu, Y. H.; Yu, Hui-Jung; Feng, Wu-Shiung
國立臺灣大學	1986	Data Path Modeling and Synthesizing for Digital Systems	Sun, L. F.; 龐台銘; 馮武雄; Sun, L. F.; Parng, Tai-Ming; Feng, Wu-Shiung
國立臺灣大學	1986	Integrated Entry and Verification System	Yuan, Y. C.; 馮武雄; 龐台銘; Yuan, Y. C.; Feng, Wu-Shiung; Parng, Tai-Ming
國立臺灣大學	1986	Off-State MOSFET's Breakdown	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1986	The Growth and Characteristics of GaAs/Ge/Si Materials	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1985-09	Automatic VLSI Circuit Synthesizer System Vol.1:A Programming Logic Array (PLA) Reduction and Generation System	馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, S. J.; Sun, L. F.

Showing items 126-175 of 190 (4 Page(s) Totally)
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