臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立臺灣大學	1989	Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme	Tsai, C. C.; 馮武雄; 陳少傑; Hsiao, P, Y.; Chen, H. F.; Tsai, C. C.; Feng, Wu-Shiung; Chen, Sao-Jie; Hsiao, P, Y.; Chen, H. F.
國立臺灣大學	1989	The Pin Alignment in VLSI Routing with Movable Terminals	Chang, K. E.; Fu, C. M.; 馮武雄; Chang, K. E.; Fu, C. M.; Feng, Wu-Shiung
臺大學術典藏	1989	Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme	Tsai, C. C.; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Tsai, C. C.; 馮武雄; 陳少傑; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie; Chen, H. F.
國立臺灣大學	1988-12	An Incremental Design Rule Checking Based on Quad Tree Representations	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1988-10	A rule-based compactor for VLSI/CAD mask layout	Hsiao, Pei-Yung; Chen, Yung Syau; Feng, Wu-Shiung; Parng, T.M.; Hsu, C.C.
國立臺灣大學	1988-06	An edge-oriented compaction scheme based on multiple storage quad tree	Hsiao, Pei-Yung; Feng, Wu-Shiung
國立臺灣大學	1988	A Global Approach for Via Minimization	Jyu, H. F.; 馮武雄; Jyu, H. F.; Feng, Wu-Shiung
國立臺灣大學	1988	A Rule-Based Compactor for VLSI/CAD Mask Layout	Hsiao, P. Y.; Syau, C. Y.; 馮武雄; 龐台銘; Hsu, C. C.; Hsiao, P. Y.; Syau, C. Y.; Feng, Wu-Shiung; Parng, Tai-Ming; Hsu, C. C.
國立臺灣大學	1988	A Rule-Based Expert System for VLSI Layout Compaction	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1988	An Edge-Oriented Compaction Scheme Based on Multiple Storage Quad Tree	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1988	The Topological Order Determination for Three-Layer Channel Routing Problem	Chang, K. E.; Lai, T. H.; 馮武雄; Chang, K. E.; Lai, T. H.; Feng, Wu-Shiung
國立臺灣大學	1987-12	A New Dynamic Switch-Box Router	Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學	1987-09	A Fault Grader	Chen, T. H.; 馮武雄; 林呈祥; Chen, T. H.; Feng, Wu-Shiung; Lin, Chen-Shang
國立臺灣大學	1987-09	Automatic Floorplan and Placement for Hierarchical Layout System	Chen, J. Y.; 馮武雄; Chen, J. Y.; Feng, Wu-Shiung
國立臺灣大學	1987-09	FAMI:A Fast Logic Minimizer for PLA Design	Maa, N. S.; 馮武雄; Maa, N. S.; Feng, Wu-Shiung
國立臺灣大學	1987-05	Hierarchical Layout System	Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; 馮武雄; Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; Feng, Wu-Shiung
國立臺灣大學	1987-05	Multi-Level Hierarchical Function Simulation	馮武雄; Lee, K. S.; Tu, H.; Feng, Wu-Shiung; Lee, K. S.; Tu, H.
國立臺灣大學	1987-05	The Multiple Storage Quad-Tree in Constraint-Graph Compaction of VLSI Layout	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1987	Extraction and Modeling of VLSI Cell Layout	Yeh, K. F.; 馮武雄; Yeh, K. F.; Feng, Wu-Shiung
國立臺灣大學	1987	HILAS-Hierarchical Interactive Layout System	Tsai, C. C.; 馮武雄; Tsai, C. C.; Feng, Wu-Shiung
國立臺灣大學	1987	Placement and Routing with Power/Ground	Chen, J. Y.; Wang, C. S.; Tseng, J. N.; 馮武雄; Chen, J. Y.; Wang, C. S.; Tseng, J. N.; Feng, Wu-Shiung
國立臺灣大學	1987	Two-Layer Corner-Stitching for Interactive Routing and Pushing of Schematic Editor	Kuop, S. T.; 馮武雄; Kuop, S. T.; Feng, Wu-Shiung
國立臺灣大學	1987	With Multiple Storage Quad Tree on the Constraint Graph Compaction of the VLSI Large-Cell Lay-Out-Editor	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1986-10	MOSFET Drain Breakdown Voltage	馮武雄; Chan, T. Y.; Hu, C.; Feng, Wu-Shiung; Chan, T. Y.; Hu, C.
國立臺灣大學	1986-09	Design and Implementation of Microprogrammed-Controller Synthesizer	于惠中; Parng, T. P.; 馮武雄; Chen, C. F.; Sun, L. F.; Yu, Hui-Jung; Parng, T. P.; Feng, Wu-Shiung; Chen, C. F.; Sun, L. F.

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