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Institution	Date	Title	Author
國立臺灣大學	1987-05	Hierarchical Layout System	Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; 馮武雄; Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; Feng, Wu-Shiung
國立臺灣大學	1987-05	Multi-Level Hierarchical Function Simulation	馮武雄; Lee, K. S.; Tu, H.; Feng, Wu-Shiung; Lee, K. S.; Tu, H.
國立臺灣大學	1987-05	The Multiple Storage Quad-Tree in Constraint-Graph Compaction of VLSI Layout	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1987	Extraction and Modeling of VLSI Cell Layout	Yeh, K. F.; 馮武雄; Yeh, K. F.; Feng, Wu-Shiung
國立臺灣大學	1987	HILAS-Hierarchical Interactive Layout System	Tsai, C. C.; 馮武雄; Tsai, C. C.; Feng, Wu-Shiung
國立臺灣大學	1987	Placement and Routing with Power/Ground	Chen, J. Y.; Wang, C. S.; Tseng, J. N.; 馮武雄; Chen, J. Y.; Wang, C. S.; Tseng, J. N.; Feng, Wu-Shiung
國立臺灣大學	1987	Two-Layer Corner-Stitching for Interactive Routing and Pushing of Schematic Editor	Kuop, S. T.; 馮武雄; Kuop, S. T.; Feng, Wu-Shiung
國立臺灣大學	1987	With Multiple Storage Quad Tree on the Constraint Graph Compaction of the VLSI Large-Cell Lay-Out-Editor	Hsiao, P. Y.; 馮武雄; Hsiao, P. Y.; Feng, Wu-Shiung
國立臺灣大學	1986-10	MOSFET Drain Breakdown Voltage	馮武雄; Chan, T. Y.; Hu, C.; Feng, Wu-Shiung; Chan, T. Y.; Hu, C.
國立臺灣大學	1986-09	Design and Implementation of Microprogrammed-Controller Synthesizer	于惠中; Parng, T. P.; 馮武雄; Chen, C. F.; Sun, L. F.; Yu, Hui-Jung; Parng, T. P.; Feng, Wu-Shiung; Chen, C. F.; Sun, L. F.
國立臺灣大學	1986-09	Design and Implementation of Schematic-Entry Generation System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Hierarchical Placement System for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	HILAS-an Hierarchical and Interactive Layout Editor System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Integrated Entry and Verification System for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Integrated VLSI Design System - Main System Design	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Layout System Vol. 4:an Automatic Placement System for VLSI Layouts	Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學	1986-09	Multiple-Level Abstraction for Hierarchical VLSI Storage System	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Netlist-Driven Cell-Layout Editor System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Private Database Management System for VLSI Design	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Three Layer Routing Algorithms for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-08	Hierarchical Timing Verification System for Multiple Clocked Logic Circuit	Tyan, C. Y.; 馮武雄; 于惠中; Yeh, T. S.; Tyan, C. Y.; Feng, Wu-Shiung; Yu, Hui-Jung; Yeh, T. S.
國立臺灣大學	1986-08	Integrated VLSI Design System:Design Entry System	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1986-08	Integrated VlSI Design System:Layout System	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1986-08	LED - A Net-List Driven Layout Editor	Jan, S. S.; Tsai, C. C.; 馮武雄; Jan, S. S.; Tsai, C. C.; Feng, Wu-Shiung
國立臺灣大學	1986-08	Schematic Layout Editor	Wang, C. I.; 馮武雄; 龐台銘; Wang, C. I.; Feng, Wu-Shiung; Parng, Tai-Ming

Showing items 141-165 of 190 (8 Page(s) Totally)
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