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Showing items 151-190 of 190 (4 Page(s) Totally)
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Institution	Date	Title	Author
國立臺灣大學	1986-09	Design and Implementation of Schematic-Entry Generation System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Hierarchical Placement System for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	HILAS-an Hierarchical and Interactive Layout Editor System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Integrated Entry and Verification System for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Integrated VLSI Design System - Main System Design	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Layout System Vol. 4:an Automatic Placement System for VLSI Layouts	Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學	1986-09	Multiple-Level Abstraction for Hierarchical VLSI Storage System	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Netlist-Driven Cell-Layout Editor System	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-09	Private Database Management System for VLSI Design	Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D.
國立臺灣大學	1986-09	Three Layer Routing Algorithms for VLSI Design	馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F.
國立臺灣大學	1986-08	Hierarchical Timing Verification System for Multiple Clocked Logic Circuit	Tyan, C. Y.; 馮武雄; 于惠中; Yeh, T. S.; Tyan, C. Y.; Feng, Wu-Shiung; Yu, Hui-Jung; Yeh, T. S.
國立臺灣大學	1986-08	Integrated VLSI Design System:Design Entry System	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1986-08	Integrated VlSI Design System:Layout System	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1986-08	LED - A Net-List Driven Layout Editor	Jan, S. S.; Tsai, C. C.; 馮武雄; Jan, S. S.; Tsai, C. C.; Feng, Wu-Shiung
國立臺灣大學	1986-08	Schematic Layout Editor	Wang, C. I.; 馮武雄; 龐台銘; Wang, C. I.; Feng, Wu-Shiung; Parng, Tai-Ming
國立臺灣大學	1986-08	Test Sequence Generator	Ou, H. C.; 馮武雄; Liaw, H. T.; Ou, H. C.; Feng, Wu-Shiung; Liaw, H. T.
國立臺灣大學	1986-08	Top-Down Placement for Hierarchical Layout System	Chang, K. E.; 馮武雄; Chang, K. E.; Feng, Wu-Shiung
國立臺灣大學	1986-05	Lattice Filter Array Implementation of Pipelined Toeplitz System Solver	Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung
國立臺灣大學	1986	An Interactive Symbolic Layout System for Integrated-Circuit Design - HISLID	馮武雄; 于惠中; Feng, Wu-Shiung; Yu, Hui-Jung
國立臺灣大學	1986	Parallel Algorithm and Architecture for Solving Covariance Eigen System	Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Jou, I. C.; Hu, Y. H.; Yu, Hui-Jung; Feng, Wu-Shiung
國立臺灣大學	1986	Data Path Modeling and Synthesizing for Digital Systems	Sun, L. F.; 龐台銘; 馮武雄; Sun, L. F.; Parng, Tai-Ming; Feng, Wu-Shiung
國立臺灣大學	1986	Integrated Entry and Verification System	Yuan, Y. C.; 馮武雄; 龐台銘; Yuan, Y. C.; Feng, Wu-Shiung; Parng, Tai-Ming
國立臺灣大學	1986	Off-State MOSFET's Breakdown	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1986	The Growth and Characteristics of GaAs/Ge/Si Materials	馮武雄; Feng, Wu-Shiung
國立臺灣大學	1985-09	Automatic VLSI Circuit Synthesizer System Vol.1:A Programming Logic Array (PLA) Reduction and Generation System	馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, S. J.; Sun, L. F.
國立臺灣大學	1985-09	Automatic VLSI Circuit Synthesizer System Vol.2:Data Path Synthesizer	馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, S. J.; Sun, L. F.
國立臺灣大學	1985-09	Automatic VLSI Circuit Synthesizer System Vol.3:Design and Imple Mentation of a Hardware Compiler Optimizer	馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, S. J.; Sun, L. F.
國立臺灣大學	1985-09	Design Verification System Vol. 1:Design and Implementation of a Mixed-Level Logic Simulator	于惠中; 龐台銘; 馮武雄; Chen, S. J.; Wu, J. K.; 于惠中; 龐台銘; Feng, Wu-Shiung; Chen, S. J.; Wu, J. K.
國立臺灣大學	1985-09	Design Verification System Vol. 2:the Knowledge-Based Microcomputer System Troubleshooter	于惠中; 龐台銘; 馮武雄; Chen, S. J.; Wu, J. K.; 于惠中; 龐台銘; Feng, Wu-Shiung; Chen, S. J.; Wu, J. K.
國立臺灣大學	1985-09	Integrated VLSI Design System - MPC Chip Design	Parng, T. P.; 于惠中; 馮武雄; Lee, J. S.; Lin, S.; Ho, H. J.; Parng, T. P.; Yu, Hui-Jung; Feng, Wu-Shiung; Lee, J. S.; Lin, S.; Ho, H. J.
國立臺灣大學	1985-09	Layout System Vol. 1:Computer-Aided VLSI Routing Design	Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學	1985-09	Layout System Vol. 3:Design and Implementation of a Design Rule Checking System for VLSI Design	Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學	1985-09	New Algorithms and Parallel VLSI Architectures for Solving Covariance System:with Application to Spectrum Estimations of Digital Signal Processing	于惠中; 龐台銘; 馮武雄; Chen, S. J.; Jou, I. C.; Sung, T. Y.; 于惠中; 龐台銘; Feng, Wu-Shiung; Chen, S. J.; Jou, I. C.; Sung, T. Y.
國立臺灣大學	1985-09	Design and Implementation of a Data Path Synthesizer for Digital System	Chu, P. C.; Sun, L. F.; 龐台銘; 于惠中; 馮武雄; Chu, P. C.; Sun, L. F.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學	1985-09	Design and Implementation of a Net-List Driven Layout System	Chen, S. J.; Shi, M. C.; Jan, S. S.; Fan, J. P.; 馮武雄; Chen, S. J.; Shi, M. C.; Jan, S. S.; Fan, J. P.; Feng, Wu-Shiung
國立臺灣大學	1985-09	The Design and Implementation of a Mixed-Level Logic Simulator	Tran, K. T.; 龐台銘; 于惠中; 馮武雄; Tyan, C. L.; Ou, H. C.; Tran, K. T.; 龐台銘; 于惠中; Feng, Wu-Shiung; Tyan, C. L.; Ou, H. C.
國立臺灣大學	1985-06	An Interactive Symbolic Layout System for Integrated-Circuit Design	馮武雄; 于惠中; Feng, Wu-Shiung; Yu, Hui-Jung
國立臺灣大學	1985	Layout System Vol. 2:Symbolic Layout and Circuit Compaction for CMOS IC Design	Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學	1985	Highly Concurrent Algorithm and Pipelined VLSI Architecture for Solving Covariance Systems	Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Jou, I. C.; Hu, Y. H.; Yu, Hui-Jung; Feng, Wu-Shiung
國立臺灣大學	1981-09	Automatic Layout System for HDTV Chip Design	楊武純; 馮武雄; Yang, Wu-Chun; Feng, Wu-Shiung

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