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Showing items 1-15 of 15 (1 Page(s) Totally)
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| 臺大學術典藏 |
2021-04-21T23:30:05Z |
Translating traditional SIMD instructions to vector length agnostic architectures
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Fu, Sheng Yu; Hsu, Wei Chung |
| 臺大學術典藏 |
2020-05-04T08:08:37Z |
SIMD Code Translation in an Enhanced HQEMU.
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Fu, Sheng-Yu; Hong, Ding-Yong; Wu, Jan-Jan; Liu, Pangfeng; Hsu, Wei-Chung; WEI-CHUNG HSU; Fu, Sheng-Yu;Hong, Ding-Yong;Wu, Jan-Jan;Liu, Pangfeng;Hsu, Wei-Chung |
| 臺大學術典藏 |
2020-05-04T08:08:36Z |
Adaptive runtime exploiting sparsity in tensor of deep learning neural network on heterogeneous systems.
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Peng, Kuo-You;Fu, Sheng-Yu;Liu, Yu-Ping;Hsu, Wei-Chung; Peng, Kuo-You; Fu, Sheng-Yu; Liu, Yu-Ping; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2020-05-04T08:08:36Z |
Exploiting Longer SIMD Lanes in Dynamic Binary Translation.
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Hong, Ding-Yong; Fu, Sheng-Yu; Liu, Yu-Ping; Wu, Jan-Jan; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2020-05-04T08:08:35Z |
Automatically Migrating Sequential Applications to Heterogeneous System Architecture.
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Liang, Chih-Yung;Fu, Sheng-Yu;Liu, Yu-Ping;Hsu, Wei-Chung; Liang, Chih-Yung; Fu, Sheng-Yu; Liu, Yu-Ping; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2020-05-04T08:08:35Z |
Dynamic tuning of applications using restricted transactional memory.
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Lin, Shih-Kai; Hong, Ding-Yong; Fu, Sheng-Yu; Wu, Jan-Jan; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2020-05-04T08:08:35Z |
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation.
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WEI-CHUNG HSU; Liu, Yu-Ping; Hong, Ding-Yong; Wu, Jan-Jan; Fu, Sheng-Yu; Hsu, Wei-Chung |
| 臺大學術典藏 |
2020-05-04T08:08:35Z |
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions.
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Fu, Sheng-Yu; Hong, Ding-Yong; Liu, Yu-Ping; Wu, Jan-Jan; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2020-05-04T08:08:35Z |
Exploiting SIMD capability in an ARMv7-to-ARMv8 dynamic binary translator.
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Fu, Sheng-Yu; Lin, Chih-Min; Hong, Ding-Yong; Liu, Yu-Ping; Wu, Jan-Jan; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2020-05-04T08:08:34Z |
Translating Traditional SIMD Instructions to Vector Length Agnostic Architectures.
|
Fu, Sheng-Yu;Hsu, Wei-Chung; Fu, Sheng-Yu; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2020-05-04T08:08:34Z |
Exploiting Vector Processing in Dynamic Binary Translation.
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Lin, Chih-Min;Fu, Sheng-Yu;Hong, Ding-Yong;Liu, Yu-Ping;Wu, Jan-Jan;Hsu, Wei-Chung; Lin, Chih-Min; Fu, Sheng-Yu; Hong, Ding-Yong; Liu, Yu-Ping; Wu, Jan-Jan; Hsu, Wei-Chung; WEI-CHUNG HSU |
| 臺大學術典藏 |
2020-05-04T08:08:22Z |
Enhancing Transactional Memory Execution via Dynamic Binary Translation
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WEI-CHUNG HSU; Hsu, Wei-Chung; Wu, Jan-Jan; Fu, Sheng-Yu; Lin, Shih-Kai; Hong, Ding-Yong; Hong, Ding-Yong;Lin, Shih-Kai;Fu, Sheng-Yu;Wu, Jan-Jan;Hsu, Wei-Chung |
| 臺大學術典藏 |
2018-09-10T08:41:17Z |
A Light charged Higgs boson in two-Higgs doublet model for CDF $Wjj$ anomaly
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Chen, Chuan-Hung;Chiang, Cheng-Wei;Nomura, Takaaki;Fu-Sheng, Yu; Chen, Chuan-Hung; Chiang, Cheng-Wei; Nomura, Takaaki; Fu-Sheng, Yu; CHENG-WEI CHIANG |
| 臺大學術典藏 |
2018-09-10T08:41:17Z |
A Light charged Higgs boson in two-Higgs doublet model for CDF $Wjj$ anomaly
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Chen, Chuan-Hung;Chiang, Cheng-Wei;Nomura, Takaaki;Fu-Sheng, Yu; Chen, Chuan-Hung; Chiang, Cheng-Wei; Nomura, Takaaki; Fu-Sheng, Yu; CHENG-WEI CHIANG |
| 臺大學術典藏 |
2015 |
SIMD Code Translation in an Enhanced HQEMU.
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Fu, Sheng-Yu; Hong, Ding-Yong; Wu, Jan-Jan; Liu, Pangfeng; Hsu, Wei-Chung; PANGFENG LIU; Fu, Sheng-Yu;Hong, Ding-Yong;Wu, Jan-Jan;Liu, Pangfeng;Hsu, Wei-Chung |
Showing items 1-15 of 15 (1 Page(s) Totally)
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