|
"guo yufeng"的相關文件
顯示項目 1-8 / 8 (共1頁)
1
每頁顯示[10|25|50]項目
| 亞洲大學 |
2013-01 |
An Analytical Model of Triple RESURF Device with Linear P?layer Doping Profile
|
Hua, Tingting;Hua, Tingting;Guo, Yufeng;Guo, Yufeng;Yu, Ying;Yu, Ying;許健;Sheu, Gene;Yao, Jiafei;Yao, Jiafei |
| 亞洲大學 |
2013-01 |
Novel Silicon-on-Insulator Lateral Power Device with Partial Oxide Pillars in the Drift Region
|
Yao, JiaFei;Yao, JiaFei;Guo, Yufeng;Guo, Yufeng;Hua, Tingting;Hua, Tingting;Huang, Shi;Huang, Shi;Zh, Changchun;Zhang, Changchun;Xia, Xiaojuan;Xia, Xiaojuan;許健;Sheu, Gene |
| 亞洲大學 |
2009.07 |
VARIATION OF LATERAL THICKNESSTECHNIQUES IN SOI LATERAL HIGH VOLTAGE DEVICE
|
郭宇鋒;Guo, Yufeng;王至剛;Wang1, Zhigong;許健;Sheu, Gene |
| 亞洲大學 |
2009-11 |
A three-dimensional breakdown model of SOI lateral power transistors with a circular layout
|
Guo, Yufeng ; Wang, Zhigong ; Sheu, Gene |
| 亞洲大學 |
2009-11 |
A Three-dimensional Breakdown Model of SOI Lateral Power Transistors with a Circular Layout
|
郭宇峰;Guo, Yufeng;Wang, Zhigong;許健;Sheu, Gene |
| 亞洲大學 |
2009-07 |
VARIATION OF LATERAL THICKNESSTECHNIQUES IN SOI LATERAL HIGH VOLTAGE DEVICE
|
郭宇鋒;Guo,Yufeng;王至剛;Wang1,Zhigong;許健;Sheu,Gene |
| 亞洲大學 |
2009-07 |
Variaton of Lateral Thickness techniques in SOI Lateral High Voltage Transistors
|
郭宇鋒;Guo, Yufeng;王至剛;Wang, Zhigong;許健;Sheu, Gene |
| 亞洲大學 |
2009 |
Variation of lateral thickness techniques in sol lateral high voltage transistors
|
Guo, Yufeng ; Wang, Zhigong ; Sheu, Gene |
顯示項目 1-8 / 8 (共1頁)
1
每頁顯示[10|25|50]項目
|
