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Showing items 1-6 of 6 (1 Page(s) Totally)
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| 臺大學術典藏 |
2020-06-29T01:20:12Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
|
Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:12Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
|
Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:09Z |
Fault Simulation and Test Generation
|
Li, J.C.-M.;Hsiao, M.S.; Li, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:09Z |
Fault Simulation and Test Generation
|
Li, J.C.-M.;Hsiao, M.S.; Li, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
|
Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
|
Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; JIUN-LANG HUANG |
Showing items 1-6 of 6 (1 Page(s) Totally)
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