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"hsieh e r"的相關文件
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| 國立交通大學 |
2020-10-05T02:01:30Z |
A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10(12) Endurance
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Hsieh, E. R.; Chang, H. Y.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert; Wong, S. Simon |
| 國立交通大學 |
2020-10-05T02:01:30Z |
Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era
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Hsieh, E. R.; Wang, H. W.; Liu, C. H.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert |
| 國立交通大學 |
2020-10-05T02:01:28Z |
Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG)
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Xiao, Y.; Hsieh, E. R.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert |
| 國立交通大學 |
2020-10-05T02:01:28Z |
High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning
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Hsieh, E. R.; Giordano, M.; Hodson, B.; Levy, A.; Osekowsky, S. K.; Radway, R. M.; Shih, Y. C.; Wan, W.; Wu, T. F.; Zheng, X.; Nelson, M.; Le, B. Q.; Wong, H. -S. P.; Mitra, S.; Wong, S. |
| 國立交通大學 |
2020-07-01T05:20:35Z |
The Demonstration of Gate Dielectric -fuse 4kb OTP Memory Feasible for Embedded Applications in High -k Metal-gate CMOS Generations and Beyond
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Hsieh, E. R.; Chang, C. W.; Chuang, C. C.; Chen, H. W.; Chung, Steve S. |
| 國立交通大學 |
2020-01-02T00:03:27Z |
The Understanding of Gate Capacitance Matching on Achieving a High Performance NC MOSFET with Sufficient Mobility
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Chiang, C. K.; Husan, P.; Lou, Y. C.; Li, F. L.; Hsieh, E. R.; Liu, C. H.; Chung, Steve S. |
| 國立交通大學 |
2019-06-03T01:09:17Z |
An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI
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Kuo, J. L.; Chen, H. W.; Hsieh, E. R.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert |
| 國立交通大學 |
2019-04-02T06:04:26Z |
A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications
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Cheng, H. W.; Hsieh, E. R.; Huang, Z. H.; Chuang, C. H.; Chen, C. H.; Li, F. L.; Lo, Y. M.; Liu, C. H.; Chung, Steve S. |
| 國立交通大學 |
2018-08-21T05:57:09Z |
The Issues on the Power Consumption of Trigate FinFET: The Design and Manufacturing Guidelines
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Chung, Steve S.; Hsieh, E. R. |
| 國立交通大學 |
2018-08-21T05:57:00Z |
The Guideline on Designing Face-tunneling FET for Large-scale-device Applications in IoT
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Hsieh, E. R.; Lee, J. W.; Lee, M. H.; Chung, Steve S. |
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