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Taiwan Academic Institutional Repository >
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"hsin shu chen"
Showing items 51-60 of 68 (7 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T14:57:27Z |
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS
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Tai, H.-Y.;Hu, Y.-S.;Chen, H.-W.;Chen, H.-S.; Tai, H.-Y.; Hu, Y.-S.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T09:47:37Z |
A 10-Bit 200 MS/s capacitor-sharing pipeline ADC
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Tseng, C.-J.;Hsieh, Y.-C.;Yang, C.-H.;Chen, H.-S.; Tseng, C.-J.; Hsieh, Y.-C.; Yang, C.-H.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A highly integrated class-D amplifier using driver delay hysteresis control
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Tai, J.-N.; Chen, H.-S.; Chiu, H.-Q.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A high-efficiency CMOS dc-dc converter with 9-μs transient recovery time
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HSIN-SHU CHEN; Chen, Jau-Horng; YI-JAN EMERY CHEN; Chen, Y.-J.E.; Chen, J.-H.; Chen, H.-S.; Tai, J.-N.; Liu, P.-J.; Ye, W.-S.; Ye, W.-S.; Tai, J.-N.; Chen, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; Liu, Pang-Jung; Ye, Wei-Shan; Tai, Jia-Nan; Chen, Hsin-Shu; Chen, Jau-Horng; Chen, Yi-Jan Emery |
| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS
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Tai, H.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC
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Tseng, C.-J.;Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Tseng, C.-J.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T09:17:42Z |
Spur-reduction design of frequency-hopping DC-DC converters
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Liu, P.-J.; Tai, J.-N.; Chen, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; YI-JAN EMERY CHEN; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T08:18:40Z |
Signal/Power integrity modeling of high-speed memory modules using chip-package-board co-analysis
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W.-D. Guo; Y.-H. Lin; H.-S. Chen; Y-C Lu; J. Hong; C.-H. Yu; A. Cheng; J. Chou; C.-J. Chang; J. Ku; T.-L. Wu; R.-B. Wu; H.-H. Chuang; YI-CHANG LU; TZONG-LIN WU; HSIN-SHU CHEN; RUEY-BEEI WU et al. |
| 臺大學術典藏 |
2018-09-10T08:14:07Z |
A fast-lock low-power subranging digital delay-locked loop
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Chen, H.-S.;Lin, J.-C.; Chen, H.-S.; Lin, J.-C.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T08:14:07Z |
A 10b 320MS/s self-calibrated pipeline ADC
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Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN |
Showing items 51-60 of 68 (7 Page(s) Totally)
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