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"hsin shu chen"的相关文件
显示项目 56-68 / 68 (共3页)
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| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC
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Tseng, C.-J.;Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Tseng, C.-J.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T09:17:42Z |
Spur-reduction design of frequency-hopping DC-DC converters
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Liu, P.-J.; Tai, J.-N.; Chen, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; YI-JAN EMERY CHEN; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T08:18:40Z |
Signal/Power integrity modeling of high-speed memory modules using chip-package-board co-analysis
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W.-D. Guo; Y.-H. Lin; H.-S. Chen; Y-C Lu; J. Hong; C.-H. Yu; A. Cheng; J. Chou; C.-J. Chang; J. Ku; T.-L. Wu; R.-B. Wu; H.-H. Chuang; YI-CHANG LU; TZONG-LIN WU; HSIN-SHU CHEN; RUEY-BEEI WU et al. |
| 臺大學術典藏 |
2018-09-10T08:14:07Z |
A fast-lock low-power subranging digital delay-locked loop
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Chen, H.-S.;Lin, J.-C.; Chen, H.-S.; Lin, J.-C.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T08:14:07Z |
A 10b 320MS/s self-calibrated pipeline ADC
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Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:00Z |
A 3mW 12b 10MS/s sub-range SAR ADC
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Chen, H.-W.;Liu, Y.-H.;Lin, Y.-H.;Chen, H.-S.; Chen, H.-W.; Liu, Y.-H.; Lin, Y.-H.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:00Z |
A 1-GS/s 6-Bit two-channel two-step ADC in 0.13-μm CMOS
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Chen, H.-W.;Chen, I.-C.;Tseng, H.-C.;Chen, H.-S.; Chen, H.-W.; Chen, I.-C.; Tseng, H.-C.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:00Z |
Characterization of 1/f noise vs. number of gate stripes in MOS transistors
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Chen; Hsin-Shu; Ito; Akira; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T07:02:57Z |
Chip-package-board co-design - A DDR3 system design example from circuit designers' perspective
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Lin, Y.-H.; Chou, J.; Lu, Y.-C.; Wu, T.-L.; Chen, H.-S.; YI-CHANG LU; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T06:30:03Z |
A self-calibrated multiphase DLL-based clock generator
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Chen, H.-S.; Hung, C.-C.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:20Z |
A 14b 20MSample/s CMOS pipelined ADC
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Chen, H.-S.; Bacrania, K.; Song, B.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2013 |
A 0.004mm2 single-channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS
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Tai, H.-Y.;Tsai, P.-Y.;Tsai, C.-H.;Chen, H.-S.; Tai, H.-Y.; Tsai, P.-Y.; Tsai, C.-H.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2005 |
A 1-V CMOS VCO for 60-GHz applications
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HSIN-SHU CHEN; YI-JAN EMERY CHEN; Heo, D.; Chen, H.-S.; Chen, Y.-J.E.; Luo, T.-N.; Bai, S.-Y. |
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