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"hsin shu chen"的相關文件
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| 臺大學術典藏 |
2018-09-10T07:36:00Z |
A 3mW 12b 10MS/s sub-range SAR ADC
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Chen, H.-W.;Liu, Y.-H.;Lin, Y.-H.;Chen, H.-S.; Chen, H.-W.; Liu, Y.-H.; Lin, Y.-H.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:00Z |
A 1-GS/s 6-Bit two-channel two-step ADC in 0.13-μm CMOS
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Chen, H.-W.;Chen, I.-C.;Tseng, H.-C.;Chen, H.-S.; Chen, H.-W.; Chen, I.-C.; Tseng, H.-C.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:00Z |
Characterization of 1/f noise vs. number of gate stripes in MOS transistors
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Chen; Hsin-Shu; Ito; Akira; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T07:02:57Z |
Chip-package-board co-design - A DDR3 system design example from circuit designers' perspective
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Lin, Y.-H.; Chou, J.; Lu, Y.-C.; Wu, T.-L.; Chen, H.-S.; YI-CHANG LU; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T06:30:03Z |
A self-calibrated multiphase DLL-based clock generator
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Chen, H.-S.; Hung, C.-C.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:20Z |
A 14b 20MSample/s CMOS pipelined ADC
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Chen, H.-S.; Bacrania, K.; Song, B.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2013 |
A 0.004mm2 single-channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS
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Tai, H.-Y.;Tsai, P.-Y.;Tsai, C.-H.;Chen, H.-S.; Tai, H.-Y.; Tsai, P.-Y.; Tsai, C.-H.; Chen, H.-S.; HSIN-SHU CHEN |
| 臺大學術典藏 |
2005 |
A 1-V CMOS VCO for 60-GHz applications
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HSIN-SHU CHEN; YI-JAN EMERY CHEN; Heo, D.; Chen, H.-S.; Chen, Y.-J.E.; Luo, T.-N.; Bai, S.-Y. |
顯示項目 61-68 / 68 (共3頁)
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