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Institution	Date	Title	Author
臺大學術典藏	2019-10-31T07:12:32Z	A 10-bit 200MS/s Capacitor-Sharing Pipeline ADC	HSIN-SHU CHEN;Hsin-Shu Chen;Ching-Hua Yang;Yi-Chun Hsieh;Chien-Jian Tseng; Chien-Jian Tseng; Yi-Chun Hsieh; Ching-Hua Yang; Hsin-Shu Chen; HSIN-SHU CHEN
臺大學術典藏	2019-10-31T07:12:32Z	A 10-bit 200MS/s Capacitor-Sharing Pipeline ADC	HSIN-SHU CHEN;Hsin-Shu Chen;Ching-Hua Yang;Yi-Chun Hsieh;Chien-Jian Tseng; Chien-Jian Tseng; Yi-Chun Hsieh; Ching-Hua Yang; Hsin-Shu Chen; HSIN-SHU CHEN
臺大學術典藏	2019-10-31T07:12:32Z	A 10-bit 200MS/s Capacitor-Sharing Pipeline ADC	HSIN-SHU CHEN;Hsin-Shu Chen;Ching-Hua Yang;Yi-Chun Hsieh;Chien-Jian Tseng; Chien-Jian Tseng; Yi-Chun Hsieh; Ching-Hua Yang; Hsin-Shu Chen; HSIN-SHU CHEN
臺大學術典藏	2019-10-31T07:12:32Z	An 8b 700MS/s 1b/cycle SAR ADC Using a Delay-Shift Technique	HSIN-SHU CHEN;Hsin-Shu Chen;Cheng-Hsueh Tsai;Pao-Yang Tsai;Hung-Yen Tai;Tsung-Han Tsai; Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen; HSIN-SHU CHEN
臺大學術典藏	2019-10-31T07:12:32Z	An 8b 700MS/s 1b/cycle SAR ADC Using a Delay-Shift Technique	HSIN-SHU CHEN;Hsin-Shu Chen;Cheng-Hsueh Tsai;Pao-Yang Tsai;Hung-Yen Tai;Tsung-Han Tsai; Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen; HSIN-SHU CHEN
臺大學術典藏	2019-10-31T07:12:32Z	An 8b 700MS/s 1b/cycle SAR ADC Using a Delay-Shift Technique	HSIN-SHU CHEN;Hsin-Shu Chen;Cheng-Hsueh Tsai;Pao-Yang Tsai;Hung-Yen Tai;Tsung-Han Tsai; Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen; HSIN-SHU CHEN
臺大學術典藏	2019-10-31T07:12:32Z	An 8b 700MS/s 1b/cycle SAR ADC Using a Delay-Shift Technique	HSIN-SHU CHEN;Hsin-Shu Chen;Cheng-Hsueh Tsai;Pao-Yang Tsai;Hung-Yen Tai;Tsung-Han Tsai; Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen; HSIN-SHU CHEN
臺大學術典藏	2019-10-15T03:05:31Z	Roles of Epstein-Barr virus viral load monitoring in the prediction of posttransplant lymphoproliferative disorder in pediatric liver transplantation	Chang, MH;YUNG-MING JENG;Hsu, HY;YEN-HSUAN NI;Chen, HL;JIA-FENG WU;REY-HENG HU;MING-CHIH HO;HSIN-SHU CHEN; HSIN-SHU CHEN; MING-CHIH HO; REY-HENG HU; JIA-FENG WU; Chen, HL; YEN-HSUAN NI; Hsu, HY; YUNG-MING JENG; Chang, MH
臺大學術典藏	2019-10-15T03:05:31Z	Roles of Epstein-Barr virus viral load monitoring in the prediction of posttransplant lymphoproliferative disorder in pediatric liver transplantation	Chang, MH;YUNG-MING JENG;Hsu, HY;YEN-HSUAN NI;Chen, HL;JIA-FENG WU;REY-HENG HU;MING-CHIH HO;HSIN-SHU CHEN; HSIN-SHU CHEN; MING-CHIH HO; REY-HENG HU; JIA-FENG WU; Chen, HL; YEN-HSUAN NI; Hsu, HY; YUNG-MING JENG; Chang, MH
臺大學術典藏	2018-09-10T15:33:01Z	An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique	Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen; HSIN-SHU CHEN; Tsung-Han Tsai;Hung-Yen Tai;Pao-Yang Tsai;Cheng-Hsueh Tsai;Hsin-Shu Chen
臺大學術典藏	2018-09-10T15:33:01Z	An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique	Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen; HSIN-SHU CHEN; Tsung-Han Tsai;Hung-Yen Tai;Pao-Yang Tsai;Cheng-Hsueh Tsai;Hsin-Shu Chen
臺大學術典藏	2018-09-10T15:33:01Z	An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique	Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen; HSIN-SHU CHEN; Tsung-Han Tsai;Hung-Yen Tai;Pao-Yang Tsai;Cheng-Hsueh Tsai;Hsin-Shu Chen
臺大學術典藏	2018-09-10T15:22:47Z	A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS	Hu, Y.-S.;Shih, C.-H.;Tai, H.-Y.;Chen, H.-W.;Chen, H.-S.; Hu, Y.-S.; Shih, C.-H.; Tai, H.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T14:57:27Z	A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS	Tai, H.-Y.;Tsai, C.-H.;Tsai, P.-Y.;Chen, H.-W.;Chen, H.-S.; Tai, H.-Y.; Tsai, C.-H.; Tsai, P.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T14:57:27Z	A 6-Bit 1 GS/s pipeline ADC using incomplete settling with background sampling-point calibration	Lai, C.-F.; Chen, H.-S.; HSIN-SHU CHEN; Tseng, C.-J.;Lai, C.-F.;Chen, H.-S.; Tseng, C.-J.
臺大學術典藏	2018-09-10T14:57:27Z	11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS	Tai, H.-Y.;Hu, Y.-S.;Chen, H.-W.;Chen, H.-S.; Tai, H.-Y.; Hu, Y.-S.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T09:47:37Z	A 10-Bit 200 MS/s capacitor-sharing pipeline ADC	Tseng, C.-J.;Hsieh, Y.-C.;Yang, C.-H.;Chen, H.-S.; Tseng, C.-J.; Hsieh, Y.-C.; Yang, C.-H.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T09:21:52Z	A highly integrated class-D amplifier using driver delay hysteresis control	Tai, J.-N.; Chen, H.-S.; Chiu, H.-Q.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T09:21:52Z	A high-efficiency CMOS dc-dc converter with 9-μs transient recovery time	HSIN-SHU CHEN; Chen, Jau-Horng; YI-JAN EMERY CHEN; Chen, Y.-J.E.; Chen, J.-H.; Chen, H.-S.; Tai, J.-N.; Liu, P.-J.; Ye, W.-S.; Ye, W.-S.; Tai, J.-N.; Chen, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; Liu, Pang-Jung; Ye, Wei-Shan; Tai, Jia-Nan; Chen, Hsin-Shu; Chen, Jau-Horng; Chen, Yi-Jan Emery
臺大學術典藏	2018-09-10T09:21:52Z	A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS	Tai, H.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T09:21:52Z	A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC	Tseng, C.-J.;Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Tseng, C.-J.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T09:17:42Z	Spur-reduction design of frequency-hopping DC-DC converters	Liu, P.-J.; Tai, J.-N.; Chen, H.-S.; Chen, J.-H.; Chen, Y.-J.E.; YI-JAN EMERY CHEN; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T08:18:40Z	Signal/Power integrity modeling of high-speed memory modules using chip-package-board co-analysis	W.-D. Guo; Y.-H. Lin; H.-S. Chen; Y-C Lu; J. Hong; C.-H. Yu; A. Cheng; J. Chou; C.-J. Chang; J. Ku; T.-L. Wu; R.-B. Wu; H.-H. Chuang; YI-CHANG LU; TZONG-LIN WU; HSIN-SHU CHEN; RUEY-BEEI WU et al.
臺大學術典藏	2018-09-10T08:14:07Z	A fast-lock low-power subranging digital delay-locked loop	Chen, H.-S.;Lin, J.-C.; Chen, H.-S.; Lin, J.-C.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T08:14:07Z	A 10b 320MS/s self-calibrated pipeline ADC	Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T07:36:00Z	A 3mW 12b 10MS/s sub-range SAR ADC	Chen, H.-W.;Liu, Y.-H.;Lin, Y.-H.;Chen, H.-S.; Chen, H.-W.; Liu, Y.-H.; Lin, Y.-H.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T07:36:00Z	A 1-GS/s 6-Bit two-channel two-step ADC in 0.13-μm CMOS	Chen, H.-W.;Chen, I.-C.;Tseng, H.-C.;Chen, H.-S.; Chen, H.-W.; Chen, I.-C.; Tseng, H.-C.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T07:36:00Z	Characterization of 1/f noise vs. number of gate stripes in MOS transistors	Chen; Hsin-Shu; Ito; Akira; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T07:02:57Z	Chip-package-board co-design - A DDR3 system design example from circuit designers' perspective	Lin, Y.-H.; Chou, J.; Lu, Y.-C.; Wu, T.-L.; Chen, H.-S.; YI-CHANG LU; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T06:30:03Z	A self-calibrated multiphase DLL-based clock generator	Chen, H.-S.; Hung, C.-C.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T03:29:20Z	A 14b 20MSample/s CMOS pipelined ADC	Chen, H.-S.; Bacrania, K.; Song, B.-S.; HSIN-SHU CHEN
臺大學術典藏	2013	A 0.004mm2 single-channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS	Tai, H.-Y.;Tsai, P.-Y.;Tsai, C.-H.;Chen, H.-S.; Tai, H.-Y.; Tsai, P.-Y.; Tsai, C.-H.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2005	A 1-V CMOS VCO for 60-GHz applications	HSIN-SHU CHEN; YI-JAN EMERY CHEN; Heo, D.; Chen, H.-S.; Chen, Y.-J.E.; Luo, T.-N.; Bai, S.-Y.

Showing items 36-68 of 68 (2 Page(s) Totally)
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