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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"hsu kc"的相关文件
显示项目 16-25 / 53 (共6页)
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| 國立交通大學 |
2014-12-08T15:42:13Z |
Characterization of porous silicate for ultra-low k dielectric application
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Liu, PT; Chang, TC; Hsu, KC; Tseng, TY; Chen, LM; Wang, CJ; Sze, SM |
| 國立交通大學 |
2014-12-08T15:41:19Z |
Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
|
Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:40:31Z |
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
|
Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:40:21Z |
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
|
Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:40:07Z |
Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection
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Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:37:23Z |
A cost-effective fast frequency-hopped code-division multiple-access light source using self-seeded Fabry-Perot laser with fiber Bragg grating array
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Peng, WR; Peng, PC; Lin, WP; Hsu, KC; Lai, YC; Chi, S |
| 國立交通大學 |
2014-12-08T15:26:37Z |
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
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Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:26:34Z |
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
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Ker, MD; Chuang, CH; Hsu, KC; Lo, WY |
| 國立交通大學 |
2014-12-08T15:26:29Z |
Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
|
Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:25:56Z |
Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-mu m CMOS integrated circuits
|
Ker, MD; Hsu, KC |
显示项目 16-25 / 53 (共6页)
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