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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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機構 日期 題名 作者
國家衛生研究院 2016-07-28 Design and synthesis of 1,2,3-triazole-containing N-acyl zanamivir analogs as potent neuraminidase inhibitors Das, A;Adak, AK;Ponnapalli, K;Lin, CH;Hsu, KC;Yang, JM;Hsu, TA;Lin, CC
國家衛生研究院 2015-12 Effect of bariatric surgery vs medical treatment on type 2 diabetes in patients with body mass index lower than 35: Five-year outcomes Hsu, CC;Almulaifi, A;Chen, JC;Ser, KH;Chen, SC;Hsu, KC;Lee, YC;Lee, WJ
國家衛生研究院 2015-06-16 Anchor-based classification and type-C inhibitors for tyrosine kinases Hsu, KC;Sung, TY;Lin, CT;Chiu, YY;Hsu, JT;Hung, HC;Sun, CM;Barve, I;Chen, WL;Huang, WC;Huang, CT;Chen, CH;Yang, JM
國立交通大學 2014-12-08T15:49:06Z Outlook for photovoltaic developments in Taiwan Hwang, HL; Hsu, KYJ; Lee, WI; Shing, YH; Hsu, KC; Tseng, BH
國立交通大學 2014-12-08T15:43:57Z Down-regulation of matrix Gla protein messenger RNA in human colorectal adenocarcinomas Fan, CW; Sheu, DL; Fan, HA; Hsu, KC; Chang, CA; Chan, EC
國立交通大學 2014-12-08T15:42:13Z Characterization of porous silicate for ultra-low k dielectric application Liu, PT; Chang, TC; Hsu, KC; Tseng, TY; Chen, LM; Wang, CJ; Sze, SM
國立交通大學 2014-12-08T15:41:19Z Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:40:31Z Latchup-free ESD protection design with complementary substrate-triggered SCR devices Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:40:21Z SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:40:07Z Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:37:23Z A cost-effective fast frequency-hopped code-division multiple-access light source using self-seeded Fabry-Perot laser with fiber Bragg grating array Peng, WR; Peng, PC; Lin, WP; Hsu, KC; Lai, YC; Chi, S
國立交通大學 2014-12-08T15:26:37Z On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:26:34Z ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process Ker, MD; Chuang, CH; Hsu, KC; Lo, WY
國立交通大學 2014-12-08T15:26:29Z Complementary substrate-triggered SCR devices for on-chip ESD protection circuits Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:25:56Z Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-mu m CMOS integrated circuits Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:25:38Z Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices Ker, MD; Chen, JH; Hsu, KC
國立交通大學 2014-12-08T15:25:22Z Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process Ker, MD; Chen, WY; Hsu, KC
國立交通大學 2014-12-08T15:25:09Z Miniaturized 3-dimensional transformer design Chen, WZ; Hsu, KC
國立交通大學 2014-12-08T15:19:14Z SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:19:08Z Fiber Bragg grating sequential UV-writing method with real-time interferometric side-diffraction position monitoring Hsu, KC; Sheu, LG; Chuang, KP; Chang, SH; Lai, YC
國立交通大學 2014-12-08T15:18:55Z Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:18:29Z Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:17:59Z Topology-aided cross-layer fast handoff designs for IEEE 802.11/Mobile IP environments Tseng, CC; Yen, LH; Chang, HH; Hsu, KC
國立交通大學 2014-12-08T15:16:51Z S-band gain-clamped grating-based erbium-doped fiber amplifier by forward optical feedback technique Yeh, CH; Lin, MC; Huang, TT; Hsu, KC; Ko, CH; Chi, S
國立交通大學 2014-12-08T15:06:13Z A NEW THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY BURIED-CHANNEL MOSFETS WU, CY; HSU, KC

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