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Taiwan Academic Institutional Repository >
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"hsu yarsun"
Showing items 1-5 of 5 (1 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:49:25Z |
DeAr: A Framework for Power-efficient and Flexible Embedded Digital Signal Processor Design
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Lee, Chi-Ming; Huang, Yong-Jyun; Liu, Chih-Wei; Hsu, Yarsun |
| 國立交通大學 |
2017-04-21T06:48:51Z |
Multi-mode message passing switch networks applied for QC-LDPC decoder
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Liu, Chih-Hao; Lin, Chien-Ching; Chang, Hsie-Chia; Lee, Chen-Yi; Hsu, Yarsun |
| 國立交通大學 |
2014-12-16T06:15:50Z |
OPERATING METHOD APPLIED TO LOW DENSITY PARITY CHECK (LDPC) DECODER AND CIRCUIT THEREOF
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LIU, Chih-Hao; Liao, Yen-Chin; Lee, Chen-Yi; Chang, Hsie-Chia; Hsu, Yarsun |
| 國立交通大學 |
2014-12-16T06:15:49Z |
MULTI-MODE MULTI-PARALLELISM DATA EXCHANGE METHOD AND DEVICE THEREOF
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LIU, Chih-Hao; Lin, Chien-Ching; Lee, Chen-Yi; Chang, Hsie-Chia; Hsu, Yarsun |
| 國立交通大學 |
2014-12-16T06:14:16Z |
Operating method and circuit for low density parity check (LDPC) decoder
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Liu Chih-Hao; Liao Yen-Chin; Lee Chen-Yi; Chang Hsie-Chia; Hsu Yarsun |
Showing items 1-5 of 5 (1 Page(s) Totally)
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