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"hsu yung lung"的相關文件
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| 國立成功大學 |
2007-02 |
Mechanism of chemical mechanical planarization induced edge corrosion of copper line for Cu/Low-k SiOC interconnects
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Hsu, Yung-Lung; Fang, Yean-Kuen; Chiang, Yen-Ting; Chou, Tse-Heng; Hong, Franklin Chau-Nan |
| 國立成功大學 |
2007-01-19 |
深次微米互補式金氧半電晶體製程影響 閘極氧化層與金屬導線可靠性的研究及模式
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許永隆; Hsu, Yung-Lung |
| 國立成功大學 |
2007-01-19 |
深次微米互補式金氧半電晶體製程影響 閘極氧化層與金屬導線可靠性的研究及模式
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許永隆; Hsu, Yung-Lung |
| 國立成功大學 |
2002-11 |
Modeling of abnormal capacitance-voltage characteristics observed in MOS transistor with ultra-thin gate oxide
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Hsu, Yung-Lung; Fang, Yean-Kuen; Tsao, Feng-Cherng; Kuo, Fu-Jung; Ho, Yens |
| 國立成功大學 |
2001-11 |
Nitrogen implanted polysilicon resistor for high-voltage CMOS technology application
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Chen, Chung-Hui; Fang, Yean-Kuen; Yang, Chih-Wei; Wang, Ta-Wei; Hsu, Yung-Lung; Hsu, Shun-Liang |
| 國立成功大學 |
2001-02 |
A novel programming technique for highly scalable and disturbance immune flash EEPROM
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Huang, Kuo-Ching; Fang, Yean-Kuen; Yaung, Dun-Nian; Chen, Chung-Hui; Hsu, Yung-Lung; Ting, Shyh-Fann; Lin, Yvonne; Kuo, Di-son; Wang, Chung S.; Liang, Mong-Song |
| 國立成功大學 |
2000-10 |
A DC current stress method to improve the voltage coefficient of resistance of the polysilicon resistor in high voltage CMOS technology
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Chen, Chung-Hui; Fang, Yean-Kuen; Kuo, Mao-Hsiung; Hsu, Yung-Lung; Hsu, Shun-Liang |
| 國立成功大學 |
2000-06-22 |
Structure for improving the characteristics of high resistivity polycrystalline resistors
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Chen, Chung-Hui; Fang, Yean-Kuen; Wang, Ta-Wei; Hsu, Yung-Lung; Hsu, Shun-Liang |
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