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机构 日期 题名 作者
臺大學術典藏 2022-09-21T23:33:19Z Variation-Tolerant Recall Operation for Nonvolatile SRAM Integrated with Ferroelectric Capacitor Li, Ai Fang; Huang, Ruei Yu; Hu, Vita Pi Ho
臺大學術典藏 2022-04-21T23:18:02Z High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing Hu, Vita Pi Ho; Liu, Chang Ju; Chiang, Hung Li; Wang, Jer Fu; Cheng, Chao Ching; TZU-CHIANG CHEN; Chang, Meng Fan
臺大學術典藏 2022-02-21T23:31:32Z 2D Materials-Based Static Random-Access Memory Liu, Chang Ju; Wan, Yi; Li, Lain Jong; Lin, Chih Pin; Hou, Tuo Hung; Huang, Zi Yuan; Hu, Vita Pi Ho
臺大學術典藏 2021-11-21T23:19:55Z Static Noise Margin Analysis for Cryo-CMOS SRAM Cell Hu, Vita Pi Ho; Liu, Chang Ju
臺大學術典藏 2021-08-22T00:00:17Z Sensitivity Analysis and Design of Negative-Capacitance Junctionless Transistor for High-Performance Applications Gupta, Manish; Hu, Vita Pi Ho
臺大學術典藏 2021-07-21T23:21:31Z Monolithic 3D SRAM cell with stacked two-dimensional materials based FETs at 2nm node Hu, Vita Pi Ho; Su, Cheng Wei; Yu, Chun Chi; Liu, Chang Ju; Weng, Cheng Yang
國立交通大學 2019-04-02T05:59:08Z Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2019-04-02T05:58:12Z Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2019-04-02T05:58:09Z Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2018-08-21T05:56:55Z Ultra-Low Voltage Mixed TFET-MOSFET 8T SRAM Cell Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:55:34Z Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET Hsu, Chih-Wei; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin
國立交通大學 2017-04-21T06:50:10Z Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:50:05Z Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-thin-body GeOI MOSFETs Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:49:57Z Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:49:47Z UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:49:09Z Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap Hu, Vita Pi-Ho; Lo, Chang-Ting; Sachid, Angada B.; Su, Pin; Hu, Chenming
國立交通大學 2017-04-21T06:49:05Z Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:49:02Z Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:48:32Z Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2016-03-28T00:04:24Z Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications Yu, Chang-Hung; Fan, Ming-Long; Yu, Kuan-Chin; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-12-02T03:00:54Z Stability/Performance Assessment of Monolithic 3D 6T/ST SRAM Cells Considering Transistor-Level Interlayer Coupling Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T11:21:14Z Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T11:20:55Z Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:31:27Z Evaluation of Read-and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:31:16Z Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:31:11Z Evaluation of Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM Cells Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:29:05Z Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET Fan, Ming-Long; Hu, Vita Pi-Ho; Hsu, Chih-Wei; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-07-21T08:28:07Z Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:38:27Z Evaluation of Static Noise Margin and Performance of 6T FinFET SRAM Cells with Asymmetric Gate to Source/Drain Underlap Devices Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:38:26Z Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs Hsieh, Chien-Yu; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:38:05Z Impact of Quantum Confinement on Short-Channel Effects for Ultrathin-Body Germanium-on-Insulator MOSFETs Wu, Yu-Sheng; Hsieh, Hsin-Yuan; Hu, Vita Pi-Ho; Su, Pin
國立交通大學 2014-12-08T15:36:58Z Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:36:16Z Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:36:11Z FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation Hu, Vita Pi-Ho; Fan, Ming-Long; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:35:52Z Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits Fan, Ming-Long; Yang, Shao-Yu; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:35:18Z Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits Yang, Shao-Yu; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:43Z Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:43Z Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs Tsai, Ming-Fu; Fan, Ming-Long; Pao, Chia-Hao; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:20Z Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:12Z Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:12Z Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:31:13Z Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:35Z Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nein; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:30Z Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:25Z Design and Analysis of Robust Tunneling FET SRAM Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:03Z A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits Pao, Chia-Hao; Fan, Ming-Long; Tsai, Ming-Fu; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:29:40Z Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:28:05Z Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic Circuits Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:25:21Z Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Region Fan, Ming-Long; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:24:25Z Investigation of Static Noise Margin of Ultra-Thin-Body SOI SRAM Cells in Subthreshold Region using Analytical Solution of Poisson's Equation Hu, Vita Pi-Ho; Wu, Yu-Sheng; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te

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