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Showing items 326-333 of 333 (34 Page(s) Totally)
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| 國立臺灣大學 |
1989-10 |
Function abstraction in automatic digital-circuit design
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Wu, J.-G.; Hu, Y.H.; Ho, W.P.-C.; Yun, D.Y.Y. |
| 國立臺灣大學 |
1989 |
A Novel Implementation of Pipelined Toeplitz System Solver
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Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1989 |
GM_Plan:A Gate Matrix Layout Algorithm Based on AI Planning Techniques
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Hu, Y. H.; 陳少傑; Hu, Y. H.; Chen, Sao-Jie |
| 國立臺灣大學 |
1989 |
GM-Learn:an Iterative Learning Algorithm for CMOS Gate Matrix Layout
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陳少傑; Hu, Y. H.; Chen, Sao-Jie; Hu, Y. H. |
| 臺大學術典藏 |
1989 |
GM-Learn:an Iterative Learning Algorithm for CMOS Gate Matrix Layout
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Hu, Y. H.; Chen, Sao-Jie; 陳少傑; Hu, Y. H.; Chen, Sao-Jie |
| 國立臺灣大學 |
1986-05 |
Lattice Filter Array Implementation of Pipelined Toeplitz System Solver
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Jou, I. C.; Hu, Y. H.; 馮武雄; Jou, I. C.; Hu, Y. H.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986 |
Parallel Algorithm and Architecture for Solving Covariance Eigen System
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Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Jou, I. C.; Hu, Y. H.; Yu, Hui-Jung; Feng, Wu-Shiung |
| 國立臺灣大學 |
1985 |
Highly Concurrent Algorithm and Pipelined VLSI Architecture for Solving Covariance Systems
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Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Jou, I. C.; Hu, Y. H.; Yu, Hui-Jung; Feng, Wu-Shiung |
Showing items 326-333 of 333 (34 Page(s) Totally)
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