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Institution	Date	Title	Author
臺大學術典藏	2018-07-06T13:43:05Z	Memory analysis and architecture for two-dimensional discrete wavelet transform	Chen, Liang-Gee; Tseng, Po-Chih; Huang, Chao-Tsung; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立政治大學	2016-06	受託義務之對象	黃朝琮; Huang, Chao-Tsung
國立高雄應用科技大學	2016	石墨應用於複合型導電高分子之電性與靜電研究	黃朝宗; HUANG, CHAO-TSUNG
國立臺灣大學	2007	On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform	Cheng, Chih-Chi; Huang, Chao-Tsung; Chen, Ching-Yeh; Lian, Chung-Jr; Chen, Liang-Gee
國立臺灣大學	2007	VLSI DESIGN OF WAVELET TRANSFORM, ANALYSIS, ARCHITECTURE, AND DESIGN EXAMPLES	Chen, Liang-Gee; Huang, Chao-Tsung; Chen, Ching-Yeh; Cheng, Chih-Chi
臺大學術典藏	2007	VLSI DESIGN OF WAVELET TRANSFORM, ANALYSIS, ARCHITECTURE, AND DESIGN EXAMPLES	Chen, Liang-Gee; Huang, Chao-Tsung; Chen, Ching-Yeh; Cheng, Chih-Chi; Chen, Liang-Gee; Huang, Chao-Tsung; Chen, Ching-Yeh; Cheng, Chih-Chi
國立臺灣大學	2006	Level C+ Data Reuse Scheme for Motion Estimation With Corresponding Coding Orders	Chen, Ching-Yeh; Huang, Chao-Tsung; Chen, Yi-Hau; Chen, Liang-Gee
國立臺灣大學	2006	High-Performance JPEG 2000 Encoder With Rate-Distortion Optimization	Fang, Hung-Chi; Chang, Yu-Wei; Wang, Tu-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2006	System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering	Chen, Ching-Yeh; Huang, Chao-Tsung; Chen, Yi-Hau; Chien, Shoa-Yi; Chen, Liang-Gee
國立臺灣大學	2005-11	Multi-mode embedded compression codec engine for power-aware video coding system	Cheng, Chih-Chi; Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2005-09	System analysis of VLSI architecture for motion-compensated temporal filtering	Chen, Ching-Yeh; Huang, Chao-Tsung; Chen, Yi-Hua; Lian, Chung-Jr; Chen, Liang-Gee
國立臺灣大學	2005-05	Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT	Cheng, Chih-Chi; Huang, Chao-Tsung; Tseng, Po-Chih; Pan, Chia-Ho; Chen, Liang-Gee
國立臺灣大學	2005-05	Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC	Chen, Tung-Chien; Huang, Yu-Wen; Tsai, Chuan-Yung; Huang, Chao-Tsung; Chen, Liang-Gee
臺大學術典藏	2005-05	Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC	Chen, Tung-Chien; Huang, Yu-Wen; Tsai, Chuan-Yung; Huang, Chao-Tsung; Chen, Liang-Gee; Chen, Tung-Chien; Huang, Yu-Wen; Tsai, Chuan-Yung; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2005-04	Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2005-04	Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2005-03	Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering	Huang, Chao-Tsung; Chen, Ching-Yeh; Chen, Yi-Hau; Chen, Liang-Gee
國立臺灣大學	2005	針對離散小波轉換以及移動補償式時間濾波之積體電路架構設計與分析	黃朝宗; Huang, Chao-Tsung
國立臺灣大學	2005	Advances in Hardware Architectures for Image and Video Coding—A Survey	Tseng, Po-Chih; Chang, Yung-Chi; Huang, Yu-Wen; Fang, Hung-Chi; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2005	VLSI Architecture for Lifting-based Shape-Adaptive Discrete Wavelet Transform with Odd-symmetric Filters	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2005	VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2005	Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2005	Reconfigurable discrete wavelet transform processor for heterogeneous reconfigurable multimedia systems	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2004-05	B-spline factorization-based architecture for inverse discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2004-05	Memory analysis and architecture for two-dimensional discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2004-05	B-spline factorization-based architecture for inverse discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2004-02	81MS/s JPEG2000 single-chip encoder with rate-distortion optimization	Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee
臺大學術典藏	2004-02	81MS/s JPEG2000 single-chip encoder with rate-distortion optimization	Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee; Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee
國立臺灣大學	2004	Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2003-09	Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2003-09	Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2003-08	VLSI architecture for discrete wavelet transform based on B-spline factorization	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2003-08	Reconfigurable discrete wavelet transform architecture for advanced multimedia systems	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
臺大學術典藏	2003-08	VLSI architecture for discrete wavelet transform based on B-spline factorization	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2003-08	Reconfigurable discrete wavelet transform architecture for advanced multimedia systems	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2002-10	Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2002-10	Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
臺大學術典藏	2002-10	Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2002-10	Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2002-05	Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2002-05	Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee

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