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显示项目 1-4 / 4 (共1页)
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| 國立交通大學 |
2015-07-21T11:20:29Z |
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells
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Luo, Shien-Chun; Chang, Kuo-Chiang; Chen, Ming-Pin; Huang, Ching-Ji; Chiu, Yi-Fang; Chen, Po-Hsun; Cheng, Liang-Chia; Liu, Chih-Wei; Chu, Yuan-Hua |
| 國立交通大學 |
2015-07-21T08:31:16Z |
An Ultra-Low Voltage Hearing Aid Chip using Variable-Latency Design Technique
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Chang, Kuo-Chiang; Luo, Shien-Chun; Huang, Ching-Ji; Liu, Chih-Wei; Chu, Yuan-Hua; Jou, Shyh-Jye |
| 淡江大學 |
2008-11 |
A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage
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Liang, Yung-chih; Huang, Ching-ji; Yang, Wei-bin |
| 淡江大學 |
2007-05 |
New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode
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Chang, Chung-yu; Yang, Wei-ben; Huang, Ching-ji; Chien, Cheng-hsing |
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