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"huang g w"的相關文件
顯示項目 26-35 / 54 (共6頁) << < 1 2 3 4 5 6 > >> 每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2018-09-10T07:03:57Z |
Micromachined 50 GHz/60 GHz Phi filters by CMOS compatible ICP deep trench technology
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Huang, P.-L.; Wang, T.; Lin, Y.-S.; Lu, S.-S.; Teng, Y.-M.; Huang, G.-W.; SHEY-SHI LU |
| 臺大學術典藏 |
2018-09-10T07:03:57Z |
Low Noise-Figure P+ AA Mesh Inductors for CMOS UWB RFIC Applications
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Huang, G.-W.; Chen, C.-Z.; Lin, Y.-S.; Lee, J.-H.; Chen, C.-C.; Lu, S.-S.; Lu, S.-S. |
| 臺大學術典藏 |
2018-09-10T05:58:41Z |
A monolithic 5.9-GHz CMOS I/Q direct-down converter utilizing a quadrature coupler and transformer-coupled subharmonic mixers
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Chen, H.-C.; Wang, T.; Lu, S.-S.; Huang, G.-W.; SHEY-SHI LU |
| 臺大學術典藏 |
2018-09-10T05:58:40Z |
Micromachined CMOS LNA and VCO by CMOS-compatible ICP deep trench technology
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Wang, T.; Chen, H.-C.; Chiu, H.-W.; Lin, Y.-S.; Huang, G.W.; Lu, S.-S.; SHEY-SHI LU |
| 臺大學術典藏 |
2018-09-10T05:58:39Z |
Reconfigurable SiGe low-noise amplifiers with variable miller capacitance
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Yang, Y.-C.; Lee, P.-W.; Chiu, H.-W.; Lin, Y.-S.; Huang, G.-W.; Lu, S.-S.; SHEY-SHI LU |
| 國立交通大學 |
2018-08-21T05:56:59Z |
Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability
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Su, C. -J.; Hong, T. -C.; Tsou, Y. -C.; Hou, F. -J.; Sung, P. -J.; Yeh, M. -S.; Wan, C. -C.; Kao, K. -H.; Tang, Y. -T.; Chiu, C. -H.; Wang, C. -J.; Chung, S. -T.; You, T. -Y.; Huang, Y. -C.; Wu, C. -T.; Lin, K. -L.; Luo, G. -L.; Huang, K. -P.; Lee, Y. -J.; Chao, T. -S.; Wu, W. -F.; Huang, G. -W.; Shieh, J. -M.; Yeh, W. -K.; Wang, Y. -H. |
| 國立交通大學 |
2018-08-21T05:56:39Z |
High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications
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Lee, Y. -J.; Hong, T. -C.; Hsueh, F. -K.; Sung, P. J.; Chen, C. -Y.; Chuang, S. -S.; Cho, T. -C.; Noda, S.; Tsou, Y. -C.; Kao, K. -H.; Wu, C. -T.; Yu, T. -Y.; Jian, Y. -L.; Su, C. -J.; Huang, Y. -M.; Huang, W. -H.; Chen, B. -Y.; Chen, M. -C.; Huang, K. -P.; Li, J. -Y.; Chen, M. -J.; Li, Y.; Samukawa, S.; Wu, W. -F.; Huang, G. -W.; Shieh, J. -M.; Tseng, T. -Y.; Chao, T. -S.; Wang, Y. -H.; Yeh, W. -K. |
| 國立交通大學 |
2017-04-21T06:49:37Z |
Pad Characterization for CMOS Technology Using Time Domain Reflectometry
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Chiu, C. S.; Chen, W. L.; Liao, K. H.; Chen, B. Y.; Teng, Y. M.; Huang, G. W.; Wu, L. K. |
| 國立成功大學 |
2017 |
High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications
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Lee, Y.-J.;Hong, T.-C.;Hsueh, F.-K.;Sung, P.-J.;Chen, Chen C.-Y.;Chuang, S.-S.;Cho, T.-C.;Noda, S.;Tsou, Y.-C.;Kao, Kao K.-H.;Wu, C.-T.;Yu, T.-Y.;Jian, Y.-L.;Su, C.-J.;Huang, Y.-M.;Huang, W.-H.;Chen, B.-Y.;Chen, M.-C.;Huang, K.-P.;Li, J.-Y.;Chen, M.-J.;Li, Y.;Samukawa, Samukawa S.;Wu, Wu W.-F.;Huang, G.-W.;Shieh, J.-M.;Tseng, Tseng T.-Y.;Chao, T.-S.;Wang, Y.-H.;Yeh, W.-K. |
| 國立成功大學 |
2017 |
Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION
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Su, C.-J.;Tang, Y.-T.;Tsou, Y.-C.;Sung, P.-J.;Hou, F.-J.;Wang, C.-J.;Chung, S.-T.;Hsieh, C.-Y.;Yeh, Yeh Y.-S.;Hsueh, F.-K.;Kao, Kao K.-H.;Chuang, S.-S.;Wu, C.-T.;You, T.-Y.;Jian, Y.-L.;Chou, T.-H.;Shen, Y.-L.;Chen, B.-Y.;Luo, G.-L.;Hong, T.-C.;Huang, K.-P.;Chen, M.-C.;Lee, Y.-J.;Chao, T.-S.;Tseng, Tseng T.-Y.;Wu, Wu W.-F.;Huang, G.-W.;Shieh, J.-M.;Yeh, W.-K.;Wang, Y.-H. |
顯示項目 26-35 / 54 (共6頁) << < 1 2 3 4 5 6 > >> 每頁顯示[10|25|50]項目
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