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Taiwan Academic Institutional Repository >
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"huang jd"
Showing items 1-10 of 34 (4 Page(s) Totally)
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| 國家衛生研究院 |
2017-08-30 |
Use of a Bayesian approach in the design and evaluation of NCE2s
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Wang, CY;Chang, LC;Lin, MS;Hsiao, CF;Huang, JD |
| 國立交通大學 |
2014-12-08T15:47:21Z |
On circuit clustering for area/delay tradeoff under capacity and pin constraints
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Huang, JD; Jou, JY; Shen, WZ; Chuang, HH |
| 國立交通大學 |
2014-12-08T15:44:59Z |
ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
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Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:44:00Z |
Unified functional decomposition via encoding for FPGA technology mapping
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Jiang, JH; Jou, JY; Huang, JD |
| 國立交通大學 |
2014-12-08T15:27:48Z |
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
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SHEN, WZ; HUANG, JD; CHAO, SM |
| 國立交通大學 |
2014-12-08T15:27:45Z |
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
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Huang, JD; Joy, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:27:41Z |
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
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Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:27:39Z |
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture
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Jiang, JH; Jou, JY; Huang, JD; Wei, JS |
| 國立交通大學 |
2014-12-08T15:27:20Z |
Compatible class encoding in hyper-function decomposition for FPGA synthesis
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Jiang, JHR; Jou, JY; Huang, JD |
| 國立交通大學 |
2014-12-08T15:25:49Z |
Verification on port connections
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Lee, GW; Wang, CY; Huang, JD; Jou, JY |
Showing items 1-10 of 34 (4 Page(s) Totally)
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