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"huang juinn dar"
Showing items 1-10 of 124 (13 Page(s) Totally)
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| 國立交通大學 |
2020-10-05T02:00:31Z |
Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs
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Song, Ling-Yen; Chen, Yi-Ling; Lei, Yung-Chun; Huang, Juinn-Dar |
| 國立交通大學 |
2020-07-01T05:21:48Z |
Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips
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Song, Ling-Yen; Li, Yu-Ying; Lei, Yung-Chun; Huang, Juinn-Dar |
| 國立交通大學 |
2020-05-05T00:02:25Z |
Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip
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Bhattacharjee, Sukanta; Wille, Robert; Huang, Juinn-Dar; Bhattacharya, Bhargab B. |
| 國立交通大學 |
2020-01-02T00:04:26Z |
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips
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Gupta, Ankur; Huang, Juinn-Dar; Yamashita, Shigeru; Roy, Sudip |
| 國立交通大學 |
2019-09-02T07:45:41Z |
Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips using Network Flow Models
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Fan, Kang-Yi; Yamashita, Shigcru; Huang, Juinn-Dar |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips
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Huang, Juinn-Dar; Liu, Chia-Hung; Yang, Wei-Hao |
| 國立交通大學 |
2019-04-02T06:04:53Z |
Graph-Based Optimal Reactant Minimization for Sample Preparation on Digital Microfluidic Biochips
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Chiang, Ting-Wei; Liu, Chia-Hung; Huang, Juinn-Dar |
| 國立交通大學 |
2019-04-02T06:04:30Z |
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays
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Wu, Chia-Cheng; Ho, Kung-Han; Huang, Juinn-Dar; Wang, Chun-Yao |
| 國立交通大學 |
2019-04-02T06:04:30Z |
Multi-Target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips
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Lei, Yung-Chun; Lin, Tien-Kuo; Huang, Juinn-Dar |
| 國立交通大學 |
2019-04-02T06:04:18Z |
Graph-Based Optimal Reactant Minimization for Sample Preparation on Digital Microfluidic Biochips
|
Chiang, Ting-Wei; Liu, Chia-Hung; Huang, Juinn-Dar |
Showing items 1-10 of 124 (13 Page(s) Totally)
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