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"huang juinn dar"
Showing items 101-110 of 124 (13 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:24:37Z |
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication
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Chen, Chien-Hua; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:23:05Z |
Thermal-Aware Logic Block Placement for 3D FPGAs Considering Lateral Heat Dissipation
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Huang, Juinn-Dar; Huang, Ya-Shih; Hsu, Mi-Yu; Chang, Han-Yuan |
| 國立交通大學 |
2014-12-08T15:22:04Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
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Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:46Z |
High-Performance NAND Flash Controller Exploiting Parallel Out-of-Order Command Execution
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Kao, Yu-Hsiang; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:46Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional Units
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Huang, Juinn-Dar; Chen, Yi-Hang; Lin, Wan-Hsien |
| 國立交通大學 |
2014-12-08T15:21:19Z |
Layer-Aware Design Partitioning for Vertical Interconnect Minimization
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Huang, Ya-Shih; Liu, Yang-Hsiang; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:19Z |
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family
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Chen, Chia-I; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Throughput Optimization for Latency-Insensitive System with Minimal Queue Insertion
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Huang, Juinn-Dar; Chen, Yi-Hang; Ho, Ya-Chien |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis
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Lee, Chi-Hui; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
Showing items 101-110 of 124 (13 Page(s) Totally)
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