| 國立交通大學 |
2014-12-08T15:24:37Z |
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication
|
Chen, Chien-Hua; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:23:05Z |
Thermal-Aware Logic Block Placement for 3D FPGAs Considering Lateral Heat Dissipation
|
Huang, Juinn-Dar; Huang, Ya-Shih; Hsu, Mi-Yu; Chang, Han-Yuan |
| 國立交通大學 |
2014-12-08T15:22:04Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:46Z |
High-Performance NAND Flash Controller Exploiting Parallel Out-of-Order Command Execution
|
Kao, Yu-Hsiang; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:46Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional Units
|
Huang, Juinn-Dar; Chen, Yi-Hang; Lin, Wan-Hsien |
| 國立交通大學 |
2014-12-08T15:21:19Z |
Layer-Aware Design Partitioning for Vertical Interconnect Minimization
|
Huang, Ya-Shih; Liu, Yang-Hsiang; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:19Z |
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family
|
Chen, Chia-I; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Throughput Optimization for Latency-Insensitive System with Minimal Queue Insertion
|
Huang, Juinn-Dar; Chen, Yi-Hang; Ho, Ya-Chien |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis
|
Lee, Chi-Hui; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:20:14Z |
CriAS: A Performance-Driven Criticality-Aware Synthesis Flow for On-Chip Multicycle Communication Architecture
|
Chen, Chia-I; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:20:13Z |
Simultaneous Data Transfer Routing and Scheduling for Interconnect Minimization in Multicycle Communication Architecture
|
Hong, Yu-Ju; Huang, Ya-Shih; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:16:33Z |
Input selection encoding for low power multiplexer tree
|
Chang, Hsiao-En; Huang, Juinn-Dar; Chen, Chia-I |
| 國立交通大學 |
2014-12-08T15:16:29Z |
Microarchitecture-aware floorplanning for processor performance optimization
|
Chen, Chi-Ying; Huang, Juinn-Dar; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-08T15:11:46Z |
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
|
Huang, Juinn-Dar; Chen, Chia-I; Lin, Yen-Ting; Hsu, Wan-Ling |
| 國立交通大學 |
2014-12-08T15:11:01Z |
Verification of pin-accurate port connections
|
Lee, Geeng-Wei; Huang, Juinn-Dar; Wang, Chun-Yao; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:10:28Z |
Reducing Fault Dictionary Size for Million-Gate Large Circuits
|
Hong, Yu-Ru; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:10:02Z |
Low-power instruction cache architecture using pre-tag checking
|
Cheng, Shi-You; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:09:35Z |
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM
|
Shih, Che-Hua; Huang, Juinn-Dar; Jon, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:24Z |
Fault dictionary size reduction for million-gate large circuits
|
Hong, Yu-Ru; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:08:23Z |
A precise bandwidth control arbitration algorithm for hard real-time SoC buses
|
Lin, Bu-Ching; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:10Z |
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
|
Huang, Ya-Shih; Hong, Yu-Ju; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:06:35Z |
A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
|
Chen, Chia-I; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:03:24Z |
A multicycle communication architecture and synthesis flow for global interconnect resource sharing
|
Huang, Wei-Sheng; Hong, Yu-Ru; Huang, Juinn-Dar; Huang, Ya-Shih |
