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Taiwan Academic Institutional Repository >
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"huang juinn dar"
Showing items 121-124 of 124 (13 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:08:23Z |
A precise bandwidth control arbitration algorithm for hard real-time SoC buses
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Lin, Bu-Ching; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:10Z |
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
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Huang, Ya-Shih; Hong, Yu-Ju; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:06:35Z |
A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
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Chen, Chia-I; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:03:24Z |
A multicycle communication architecture and synthesis flow for global interconnect resource sharing
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Huang, Wei-Sheng; Hong, Yu-Ru; Huang, Juinn-Dar; Huang, Ya-Shih |
Showing items 121-124 of 124 (13 Page(s) Totally)
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