| 國立交通大學 |
2014-12-08T15:48:25Z |
FSM-Based Formal Compliance Verification of Interface Protocols
|
Shih, Che-Hua; Yang, Ya-Ching; Yen, Chia-Chih; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:47:36Z |
Cycle-Time-Aware Sequential Way-Access Set-Associative Cache for Low Energy Consumption
|
Ting, Chih-Hui; Huang, Juinn-Dar; Kao, Yu-Hsiang |
| 國立交通大學 |
2014-12-08T15:47:29Z |
Low Power Multiplexer Tree Design Using Dynamic Propagation Path Control
|
Li, Nan-Shing; Huang, Juinn-Dar; Huang, Han-Jung |
| 國立交通大學 |
2014-12-08T15:41:11Z |
Efficient Two-Layered Cycle-Accurate Modeling Technique for Processor Family with Same Instruction Set Architecture
|
Chiang, Chien-De; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:37:00Z |
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication
|
Lin, Bu-Ching; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:36:34Z |
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors
|
Lin, Bu-Ching; Shih, Ming-En; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:34:50Z |
Sample Preparation for Many-Reactant Bioassay on DMFBs using Common Dilution Operation Sharing
|
Liu, Chia-Hung; Chang, Hao-Han; Liang, Tung-Che; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:32:21Z |
Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips
|
Huang, Juinn-Dar; Liu, Chia-Hung; Lin, Huei-Shan |
| 國立交通大學 |
2014-12-08T15:30:08Z |
Reactant Minimization during Sample Preparation on Digital Microfluidic Biochips using Skewed Mixing Trees
|
Huang, Juinn-Dar; Liu, Chia-Hung; Chiang, Ting-Wei |
| 國立交通大學 |
2014-12-08T15:24:37Z |
FSM-based transaction-level functional coverage for interface compliance verification
|
Su, Man-Yun; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:24:37Z |
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication
|
Chen, Chien-Hua; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:23:05Z |
Thermal-Aware Logic Block Placement for 3D FPGAs Considering Lateral Heat Dissipation
|
Huang, Juinn-Dar; Huang, Ya-Shih; Hsu, Mi-Yu; Chang, Han-Yuan |
| 國立交通大學 |
2014-12-08T15:22:04Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:46Z |
High-Performance NAND Flash Controller Exploiting Parallel Out-of-Order Command Execution
|
Kao, Yu-Hsiang; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:46Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional Units
|
Huang, Juinn-Dar; Chen, Yi-Hang; Lin, Wan-Hsien |
| 國立交通大學 |
2014-12-08T15:21:19Z |
Layer-Aware Design Partitioning for Vertical Interconnect Minimization
|
Huang, Ya-Shih; Liu, Yang-Hsiang; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:19Z |
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family
|
Chen, Chia-I; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Throughput Optimization for Latency-Insensitive System with Minimal Queue Insertion
|
Huang, Juinn-Dar; Chen, Yi-Hang; Ho, Ya-Chien |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis
|
Lee, Chi-Hui; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:20:14Z |
CriAS: A Performance-Driven Criticality-Aware Synthesis Flow for On-Chip Multicycle Communication Architecture
|
Chen, Chia-I; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:20:13Z |
Simultaneous Data Transfer Routing and Scheduling for Interconnect Minimization in Multicycle Communication Architecture
|
Hong, Yu-Ju; Huang, Ya-Shih; Huang, Juinn-Dar |
| 國立交通大學 |
2014-12-08T15:16:33Z |
Input selection encoding for low power multiplexer tree
|
Chang, Hsiao-En; Huang, Juinn-Dar; Chen, Chia-I |
| 國立交通大學 |
2014-12-08T15:16:29Z |
Microarchitecture-aware floorplanning for processor performance optimization
|
Chen, Chi-Ying; Huang, Juinn-Dar; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-08T15:11:46Z |
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
|
Huang, Juinn-Dar; Chen, Chia-I; Lin, Yen-Ting; Hsu, Wan-Ling |
