| 臺大學術典藏 |
2020-04-16T02:36:10Z |
A new approach to schedule operations across nested-ifs and nested-loops.
|
Huang, Shih-Hsu; Hwang, Cheng-Tsung; Hsu, Yu-Chin; Oyang, Yen-Jen; YEN-JEN OYANG |
| 臺大學術典藏 |
2018-07-05T01:55:30Z |
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits
|
Huang, Shih-Hsu; Hsu, Yu-Chin; Oyang, Yen-Jen; Huang, Shih-Hsu; Hsu, Yu-Chin; Oyang, Yen-Jen |
| 中原大學 |
2009-05 |
Minimum-Power Clock Gating
|
Jian, Jia-Hong;Cheng, Chun-Hua;Chang, Chia-Ming;Huang, Shih-Hsu |
| 中原大學 |
2007-12 |
A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs
|
Huang, Shih-Hsu;Wang, Chu-Liao;Huang, Man-Lin |
| 中原大學 |
2007-10 |
Utilizing Clock Skew for Timing Reliability Improvement
|
Huang, Shih-Hsu;Lin, Yu-Hui;Huang, Man-Lin |
| 中原大學 |
2006-10 |
High-Speed Fuzzy Inference Processor Using Active Rules Identification
|
Huang, Shih-Hsu;Liu, Shi-Zhi;Chen, Yi-Rung;Lai, Jian-Yuan |
| 中原大學 |
2006-10 |
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
|
Huang, Shih-Hsu;Cheng, Chun-Hua;Chiang, Chung-Hsin;Chang, Chia-Ming |
| 中原大學 |
2006-08 |
Register Binding for Clock Skew Optimization
|
Huang, Shih-Hsu;Cheng, Chun-Hua;Nieh, Yow-Tyng;Yu, Wei-Chieh |
| 中原大學 |
2006-08 |
Simultaneous Application of Operation Scheduling and Power Management
|
Huang, Shih-Hsu;Cheng, Chun-Hua;Chiang, Chung-Hsin;Chang, Chia-Ming |
| 中原大學 |
2006-06 |
Heat-Driven Functional Unit Binding
|
Yu, Wei-Chieh;Huang, Shih-Hsu |
| 中原大學 |
2006-06 |
New 2-D Adaptive Filter for Y/C Separation in Composite Signals
|
Lin, Chun-Hung;Huang, Shih-Hsu |
| 中原大學 |
2006-06 |
同時進行運算排序及運算時間選擇以最小化週期與週期間的功率差異 Simultaneous Operation Scheduling and Operation Delay Selection for Minimizing Cycle-By-Cycle Power Differential
|
Yen, Wei-Ting;Huang, Shih-Hsu;Cheng, Chun-Hua |
| 中原大學 |
2005-05 |
Simultaneous Clock Selection and Operation Scheduling for Multi-Cycle Communication
|
Huang, Shih-Hsu;Chiang, Chung-Hsin;Cheng, Chun-Hua |
| 中原大學 |
2004-12 |
A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities
|
Huang, Shih-Hsu;Lai, Jian-Yuan |
| 中原大學 |
2004-12 |
Downlink Base Transmit Station Modulator in WCDMA System
|
Bai, Kai-Hao;Huang, Shih-Hsu |
| 中原大學 |
2004-06 |
用於網路封包分類器的特殊用途內容定址記憶體
|
黃世旭;李龍恩;黃曼玲 ;Huang, Shih-Hsu;Lee, Long-En;Huang, Man-Lin |
| 中原大學 |
2003-12 |
Clock Skew Scheduling for Peak Current Minimization
|
Chang, Chia-Ming;Huang, Shih-Hsu;Nieh, Yow-Tyng |
| 中原大學 |
2003-08 |
Process-Variation-Tolerant Clock Tree Design Methodology
|
Huang, Shih-Hsu;Lin, Yu-Hui;Nieh, Yow-Tyng |
| 中原大學 |
2002-11 |
A High Speed Fuzzy Infernece Processor with Dynamic Scheduling Capability
|
Huang, Shih-Hsu;Lai, Jian-Yuan |
| 中原大學 |
2002-08 |
Clock Period Minimization by Incorporating Clock Skew Scheduling and Gate-Level Delay Insertion
|
Huang, Shih-Hsu;Nieh, Yow-Tyng |
| 中原大學 |
2002-08 |
Performance and Power Driven Non-Zero Skew Clock Tree Design Methodology
|
Huang, Shih-Hsu;Lin, Yu-Hui |
| 中原大學 |
2001-05 |
An Efficient Membership Function Representation for High-Resolution Fuzzy Systems
|
Huang, Shih-Hsu;Lai, Jian-Yuan |
| 中原大學 |
2000-12 |
An Interconnect-Driven Low Power Design Methodology
|
Huang, Shih-Hsu;Hsiao, Hsu-Ming |
| 中原大學 |
2000-08 |
A New Scheduling Algorithm for Automatic Synthesis of the Control Blocks of Multi-way Branch Architectures
|
Huang, Shih-Hsu |
| 中原大學 |
1999-12 |
A Practical Clock Tree Synthesis Flow
|
Chi, Chen Mely;Huang, Shih-Hsu |
| 中原大學 |
1999-12 |
A Practical Clock Tree Synthesis Flow
|
Chi, Mely-Chen;Huang, Shih-Hsu |
| 國立臺灣大學 |
1995 |
A new approach to schedule operations across nested-ifs and nested-loops
|
Huang, Shih-Hsu; Hwang, Cheng-Tsung; Hsu, Yu-Chin; Oyang, Yen-Jen |
| 國立臺灣大學 |
1995 |
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits
|
Huang, Shih-Hsu; Hsu, Yu-Chin; Oyang, Yen-Jen |
| 臺大學術典藏 |
1995 |
A new approach to schedule operations across nested-ifs and nested-loops
|
Huang, Shih-Hsu; Hwang, Cheng-Tsung; Hsu, Yu-Chin; Oyang, Yen-Jen; Huang, Shih-Hsu; Hwang, Cheng-Tsung; Hsu, Yu-Chin; Oyang, Yen-Jen |
| 臺大學術典藏 |
1995 |
Synthesis of false loop free circuits.
|
Huang, Shih-Hsu; Liu, Ta-Yung; Hsu, Yu-Chin; Oyang, Yen-Jen; YEN-JEN OYANG |
