| 國立彰化師範大學 |
2009-08 |
Distribution-Compensable Jitter Generator for Communication Test
|
Chou, Yi-Hsien; Wu, Tsu-Hsin; Chen, Pin-Chung; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2009-07 |
Low-Cost CLT-based Random Number Generator for Communication Test
|
Chou, Yi-Hsien; Wu, Tsu-Hsin; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2009-06 |
Low-Cost Fast Distribution-Programmable Jitter Generators for Communication Test
|
Chou, Yi-Hsian; Fen, Sheng-Jie; Wu, Tsu-Hsin; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2009-05 |
Inverting Techniques for Low-Power Dependable Fully-Asymmetric Communication and Storage Systems
|
Liu, Choa-Nan; Lo, Shih-Chuan; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2009 |
Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency
|
Hsu, Wei-Ning; Wu, Tsu-Hsin; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-10 |
A Low-Power Dependable Berger Code for Fully Asymmetric Communication
|
Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-10 |
A Low-Cost and Fast Normal-Distribution Random Number Generator
|
Hou, Hsiao-Han; Chou, Yi-Hsien; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-10 |
Berger Inver Codes: A Low-Power Dependable Code for Fully Asymmetric Communication
|
Liu, Choa-Nan; Lin, Shun-Dao; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-08 |
Area-Efficient True One-Period Delayline for Cycle-to-Cycle Jitter Measurement
|
Yang, Cheng-Han; Chou, Yi-Hsian; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-07 |
Area-Efficient True One-Period Delay Jitter Measurement
|
Yang, Cheng-Han; Chou, Yi-Hsian; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-07 |
A Novel Adaptive-Data-Retention CMOS Logic Structure for IDDS Test
|
Chen, Hsin-Ling; Li, Ling; Liu, Choa-Nan; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-07 |
MTCMOS SRAM Design for Data-Retention and High-Resolution Current Test
|
Chen, Chih-Jong; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-06 |
Low-Power High-Speed High-Current-Testability Cell-Based Design Automation
|
Chen, Hsin-Ling; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2007-12 |
Power-Gating Current Test for Static RAM in Nanotechnologies
|
Chao, Yuan-Wei; Chen, Hsin-Ling; Chen, Chih-Jong; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2007-11 |
Design for Fast and High-Resolution Current Testability of SRAM in Nanotechnology
|
Chao, Yuan-Wei; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2007-08 |
A Single-Clock Enhanced Random Access Scan
|
Chen, Chen-An; He, Wei-Yi; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2007-05 |
Congruence Synchronous Mirror Delay
|
Huang, Tsung-Chu; Chang, Gau-Bin; Li, Ling |
| 國立彰化師範大學 |
2006-10 |
A High-Resolution Current Test Scheme for Nanotechnologies
|
Huang, Tsung-Chu; Li, Ling |
| 國立彰化師範大學 |
2006-08 |
IDDS Testing for Nanotechnologies
|
Huang, Tsung-Chu; Li, Ling; Chao, Yuan-Wei |
| 國立彰化師範大學 |
2006-04 |
A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling
|
Huang, Tsung-Chu; Tzeng, Jing-Chi; Chao, Yuan-Wei; Chen, Ji-Jan; Liu, Wei-Ting; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2005-11 |
Vector Control Technique and Sleep-Transistor Allocation for Supply-Gating Current Spike Reduction in Power Management
|
Tzeng, Jing-Chi; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2005-08 |
A Low-Area Digital Synchronous Mirror Delay
|
Chang, Gau-Bin; Tzeng, Jing-Chi; Huang, Tsung-Chu |
| 國立成功大學 |
2002-12 |
An interleaving technique for reducing peak power in multiple-chain scan circuits during test application
|
Lee, Kuen-Jong; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2002-12 |
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application
|
Lee, Kuen-Jong; Huang, Tsung-Chu |
| 國立成功大學 |
2001-07 |
Reduction of power consumption in scan-based circuits during test application by an input control technique
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2001-07 |
Reduction of Power Consumption in Scan-based Circuits During Test Application by an Input Control Technique
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立成功大學 |
2001-05-24 |
Token scan cell for low power testing
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2001-05 |
Token Scan Cell for Low Power Testing
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2001 |
A Token Scan Architecture for Low Power Testing
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2001 |
A Low-Power LFSR Architecture
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2000 |
Peak-power Reduction for Multiple-scan Circuits During Test Application
|
Lee, Kuen-Jong; Huang, Tsung-Chu; Chen, Jih-Jeen |
| 國立彰化師範大學 |
1999-04 |
BIFEST: A Built-in Intermediate Fault Effect Sensing and Test Generation System for Cmos Bridging Faults
|
Lee, Kuen-Jong; Tang, Jing-Jou; Huang, Tsung-Chu |
| 國立彰化師範大學 |
1999 |
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
1997 |
A High-Speed Low-Voltage Built-In Current Sensor
|
Huang, Tsung-Chu; Huang, Min-Cheng; Lee, Kuen-Jong |
| 國立彰化師範大學 |
1997 |
Built-In Current Sensor Designs Based on the Bulk-Driven Technique
|
Huang, Tsung-Chu; Huang, Min-Cheng; Lee, Kuen-Jong |
| 國立彰化師範大學 |
1996 |
Combination of Automatic Test Pattern Generation and Built-in Intermediate Voltage Sensing for Detecting CMOS Bridging Faults
|
Lee, Kuen-Jong; Tang, Jing-Jou; Huang, Tsung-Chu; Tsai, Cheng-Liang |
