| 國立彰化師範大學 |
2007-08 |
A Single-Clock Enhanced Random Access Scan
|
Chen, Chen-An; He, Wei-Yi; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2007-05 |
Congruence Synchronous Mirror Delay
|
Huang, Tsung-Chu; Chang, Gau-Bin; Li, Ling |
| 國立彰化師範大學 |
2006-10 |
A High-Resolution Current Test Scheme for Nanotechnologies
|
Huang, Tsung-Chu; Li, Ling |
| 國立彰化師範大學 |
2006-08 |
IDDS Testing for Nanotechnologies
|
Huang, Tsung-Chu; Li, Ling; Chao, Yuan-Wei |
| 國立彰化師範大學 |
2006-04 |
A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling
|
Huang, Tsung-Chu; Tzeng, Jing-Chi; Chao, Yuan-Wei; Chen, Ji-Jan; Liu, Wei-Ting; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2005-11 |
Vector Control Technique and Sleep-Transistor Allocation for Supply-Gating Current Spike Reduction in Power Management
|
Tzeng, Jing-Chi; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2005-08 |
A Low-Area Digital Synchronous Mirror Delay
|
Chang, Gau-Bin; Tzeng, Jing-Chi; Huang, Tsung-Chu |
| 國立成功大學 |
2002-12 |
An interleaving technique for reducing peak power in multiple-chain scan circuits during test application
|
Lee, Kuen-Jong; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2002-12 |
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application
|
Lee, Kuen-Jong; Huang, Tsung-Chu |
| 國立成功大學 |
2001-07 |
Reduction of power consumption in scan-based circuits during test application by an input control technique
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2001-07 |
Reduction of Power Consumption in Scan-based Circuits During Test Application by an Input Control Technique
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立成功大學 |
2001-05-24 |
Token scan cell for low power testing
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2001-05 |
Token Scan Cell for Low Power Testing
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2001 |
A Token Scan Architecture for Low Power Testing
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2001 |
A Low-Power LFSR Architecture
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
2000 |
Peak-power Reduction for Multiple-scan Circuits During Test Application
|
Lee, Kuen-Jong; Huang, Tsung-Chu; Chen, Jih-Jeen |
| 國立彰化師範大學 |
1999-04 |
BIFEST: A Built-in Intermediate Fault Effect Sensing and Test Generation System for Cmos Bridging Faults
|
Lee, Kuen-Jong; Tang, Jing-Jou; Huang, Tsung-Chu |
| 國立彰化師範大學 |
1999 |
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
|
Huang, Tsung-Chu; Lee, Kuen-Jong |
| 國立彰化師範大學 |
1997 |
A High-Speed Low-Voltage Built-In Current Sensor
|
Huang, Tsung-Chu; Huang, Min-Cheng; Lee, Kuen-Jong |
| 國立彰化師範大學 |
1997 |
Built-In Current Sensor Designs Based on the Bulk-Driven Technique
|
Huang, Tsung-Chu; Huang, Min-Cheng; Lee, Kuen-Jong |
| 國立彰化師範大學 |
1996 |
Combination of Automatic Test Pattern Generation and Built-in Intermediate Voltage Sensing for Detecting CMOS Bridging Faults
|
Lee, Kuen-Jong; Tang, Jing-Jou; Huang, Tsung-Chu; Tsai, Cheng-Liang |
