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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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機構 日期 題名 作者
國立成功大學 2011-09 Origin of Stress Memorization Mechanism in Strained-Si nMOSFETs Using a Low-Cost Stress-Memorization Technique Huang, Yao-Tsung; Wu, San-Lein; Chang, Shoou-Jinn; Kuo, Cheng-Wen; Chen, Ya-Ting; Cheng, Yao-Chin; Cheng, Osbert
國立成功大學 2011-07-22 增進載子遷移率技術在次45奈米金氧半電晶體元件應用之研究 黃耀聰; Huang, Yao-Tsung
國立成功大學 2011-07-08 增進載子遷移率技術在次45奈米金氧半電晶體元件應用之研究 黃耀聰; Huang, Yao-Tsung
國立成功大學 2011-06 Temperature Dependence of Electrical Characteristics of Strained nMOSFETs Using Stress Memorization Technique Huang, Po Chin; Wu, San Lein; Chang, Shoou Jinn; Kuo, Cheng Wen; Chang, Ching Yao; Huang, Yao Tsung; Cheng, Yao Chin; Cheng, Osbert
國立成功大學 2011-06 Characteristics of Si/SiO(2) Interface Properties for CMOS Fabricated on Hybrid Orientation Substrate Using Amorphization/Templated Recrystallization (ATR) Method Huang, Po Chin; Wu, San Lein; Chang, Shoou Jinn; Huang, Yao Tsung; Chen, Jone F.; Lin, Chien Ting; Ma, Mike; Cheng, Osbert
國立成功大學 2011-05 Enhancement of CMOSFETs Performance by Utilizing SACVD-Based Shallow Trench Isolation for the 40-nm Node and Beyond Huang, Yao-Tsung; Wu, San-Lein; Chang, Shoou-Jinn; Hung, Chin-Kai; Wang, Tzu-Juei; Kuo, Cheng-Wen; Huang, Cheng-Tung; Cheng, Osbert
國立成功大學 2011-04 Investigation of stress memorization process on low-frequency noise performance for strained Si n-type metal-oxide-semiconductor field-effect transistors Kuo, Cheng-Wen;Wu, San-Lein;Lin, Hau-Yu;Huang, Yao-Tsung;Chang, Shoou-Jinn;Hong, De-Gong;Wu, Chung-Yi;Cheng, Yao-Chin;Cheng, Osbert
國立成功大學 2011-03-15 Effect of annealing time on Si/SiO(2) interface property for CMOS fabricated on hybrid orientation substrate with ATR method Huang, Po Chin; Wu, San Lein; Chang, Shoou Jinn; Huang, Yao Tsung; Lin, Chien Ting; Ma, Mike; Cheng, Osbert
國立成功大學 2007-09 CMOS dual-work-function engineering by using implanted Ni-FUSI Lin, Chien-Ting; Ramin, Manfred; Pas, Michael; Wise, Rick; Fang, Yean-Kuen; Hsu, Che-Hua; Huang, Yao-Tsung; Cheng, Li-Wei; Ma, Mike
國立成功大學 2007-04 Extra bonus on transistor optimization with stress enhanced notched-gate technology for sub-90 nm complementary metal oxide semiconductor field effect transistor Lin, Chien-Ting; Fang, Yean-Kuen; Lai, Chieh-Ming; Yeh, Wen-Kuan; Hsu, Che-Hua; Cheng, Li-Wei; Huang, Yao-Tsung; Ma, Guang Hwa

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