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Showing items 1-13 of 13 (1 Page(s) Totally)
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| 國立交通大學 |
2020-10-05T02:02:02Z |
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices
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Kingra, Sandeep Kaur; Parmar, Vivek; Chang, Che-Chia; Hudec, Boris; Hou, Tuo-Hung; Suri, Manan |
| 國立交通大學 |
2020-03-01 |
Semi-Empirical RC Circuit Model for Non-Filamentary Bi-Layer OxRAM Devices
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Suri, Manan; Majumdar, Swatilekha; Chen, Ying; Hudec, Boris; Hou, Tuo-Hung |
| 國立交通大學 |
2019-04-02T06:04:37Z |
Interchangeable Hebbian and Anti-Hebbian STDP Applied to Supervised Learning in Spiking Neural Network
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Chang, Che-Chia; Chen, Pin-Chun; Hudec, Boris; Liu, Po-Tsun; Hou, Tuo-Hung |
| 國立交通大學 |
2019-04-02T06:04:32Z |
Three dimensional integration of ReRAMs
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Hudec, Boris; Chang, Che-Chia; Wang, I-Ting; Frohlich, Karol; Hou, Tuo-Hung |
| 國立交通大學 |
2019-04-02T06:04:27Z |
Memristive devices by ALD: design aspects for high density 3D arrays for memory and neuromorphic applications
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Hudec, Boris; Chang, Che-Chia; Hou, Tuo-Hung |
| 國立交通大學 |
2019-04-02T06:01:02Z |
Recommended Methods to Study Resistive Switching Devices
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Lanza, Mario; Wong, H-S Philip; Pop, Eric; Ielmini, Daniele; Strukov, Dimitri; Regan, Brian C.; Larcher, Luca; Villena, Marco A.; Yang, J. Joshua; Goux, Ludovic; Belmonte, Attilio; Yang, Yuchao; Puglisi, Francesco M.; Kang, Jinfeng; Magyari-Kope, Blanka; Yalon, Eilam; Kenyon, Anthony; Buckwell, Mark; Mehonic, Adnan; Shluger, Alexander; Li, Haitong; Hou, Tuo-Hung; Hudec, Boris; Akinwande, Deji; Ge, Ruijing; Ambrogio, Stefano; Roldan, Juan B.; Miranda, Enrique; Sune, Jordi; Pey, Kin Leong; Wu, Xing; Raghavan, Nagarajan; Wu, Ernest; Lu, Wei D.; Navarro, Gabriele; Zhang, Weidong; Wu, Huaqiang; Li, Runwei; Holleitner, Alexander; Wurstbauer, Ursula; Lemme, Max C.; Liu, Ming; Long, Shibing; Liu, Qi; Lv, Hangbing; Padovani, Andrea; Pavan, Paolo; Valov, Ilia; Jing, Xu; Han, Tingting; Zhu, Kaichen; Chen, Shaochuan; Hui, Fei; Shi, Yuanyuan |
| 國立交通大學 |
2018-08-21T05:56:59Z |
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
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Chang, Chih-Cheng; Liu, Jen-Chieh; Shen, Yu-Lin; Chou, Teyuh; Chen, Pin-Chun; Wang, I-Ting; Su, Chih-Chun; Wu, Ming-Hong; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Wong, H-S Philip; Hou, Tuo-Hung |
| 國立交通大學 |
2018-08-21T05:53:31Z |
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
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Chang, Chih-Cheng; Chen, Pin-Chun; Chou, Teyuh; Wang, I-Ting; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Hou, Tuo-Hung |
| 國立交通大學 |
2018-08-21T05:53:09Z |
Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication
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Chen, Hong-Yu; Brivio, Stefano; Chang, Che-Chia; Frascaroli, Jacopo; Hou, Tuo-Hung; Hudec, Boris; Liu, Ming; Lv, Hangbing; Molas, Gabriel; Sohn, Joon; Spiga, Sabina; Teja, V. Mani; Vianello, Elisa; Wong, H. -S. Philip |
| 國立交通大學 |
2018-08-21T05:52:51Z |
Internal current amplification induced by dielectric hole trapping in monolayer MoS2 transistor
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Liu, Pang-Shiuan; Lin, Ching-Ting; Hudec, Boris; Hou, Tuo-Hung |
| 國立交通大學 |
2017-04-21T06:56:24Z |
Interface engineered HfO2-based 3D vertical ReRAM
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Hudec, Boris; Wang, I-Ting; Lai, Wei-Li; Chang, Che-Chia; Jancovic, Peter; Frohlich, Karol; Micusik, Matej; Omastova, Maria; Hou, Tuo-Hung |
| 國立交通大學 |
2017-04-21T06:56:16Z |
3D resistive RAM cell design for high-density storage class memory-a review
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Hudec, Boris; Hsu, Chung-Wei; Wang, I-Ting; Lai, Wei-Li; Chang, Che-Chia; Wang, Taifang; Frohlich, Karol; Ho, Chia-Hua; Lin, Chen-Hsi; Hou, Tuo-Hung |
| 國立交通大學 |
2016-03-28T00:05:42Z |
Crossbar array of selector-less TaOx/TiO2 bilayer RRAM
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Chou, Chun-Tse; Hudec, Boris; Hsu, Chung-Wei; Lai, Wei-Li; Chang, Chih-Cheng; Hou, Tuo-Hung |
Showing items 1-13 of 13 (1 Page(s) Totally)
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