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Taiwan Academic Institutional Repository >
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"hwang wei"
Showing items 146-155 of 202 (21 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:46:20Z |
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
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Chuang, Li-Pu; Chang, Ming-Hung; Huang, Po-Tsang; Kan, Chih-Hao; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:46:19Z |
"Green" micro-architecture and circuit co-design for ternary content addressable memory
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Huang, Po-Tsang; Chang, Shu-Wei; Liu, Wen-Yen; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:57Z |
A 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-Calibration
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Chang, Ming-Hung; Chuang, Li-Pu; Chang, I-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:56Z |
IN-SITU SELF-AWARE ADAPTIVE POWER CONTROL SYSTEM WITH MULTI-MODE POWER GATING NETWORK
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Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:55Z |
A ROBUST ULTRA-LOW POWER ASYNCHRONOUS FIFO MEMORY WITH SELF-ADAPTIVE POWER CONTROL
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Chang, Mu-Tien; Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:38:51Z |
Fully On-Chip Temperature, Process, and Voltage Sensors
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Chen, Shi-Wen; Chang, Ming-Hung; Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:38:49Z |
Low Quiescent Current Variable Output Digital Controlled Voltage Regulator
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Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:37:44Z |
Impacts of gate-oxide breakdown on power-gated SRAM
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Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:37:31Z |
A 65 nm 0.165 fJ/Bit/Search 256 x 144 TCAM Macro Design for IPv6 Lookup Tables
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Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:35:47Z |
Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications
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Huang, Teng-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Chen, Kuan-Neng; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei |
Showing items 146-155 of 202 (21 Page(s) Totally)
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