| 國立交通大學 |
2014-12-08T15:31:09Z |
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices
|
Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:31:08Z |
Adaptive Power Control Technique on Power-Gated Circuitries
|
Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:30:49Z |
Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration
|
Chiang, Cheng-Hao; Hu, Yu-Chen; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:30:49Z |
Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations
|
Hu, Yu-Chen; Chiang, Cheng-Hao; Chen, Kuo-Hua; Chiu, Chi-Tsung; Chuang, Ching-Te; Hwang, Wei; Chiou, Jin-Chern; Tong, Ho-Ming; Chen, Kuan-Neng |
| 國立交通大學 |
2014-12-08T15:30:06Z |
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
|
Yang, Hao-I; Lin, Yi-Wei; Hsia, Mao-Chih; Lin, Geng-Cing; Chang, Chi-Shin; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:30:05Z |
Substrate Noise Suppression Technique for Power Integrity of TSV 3D Integration
|
Yang, Po-Jen; Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
|
Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:40Z |
TIMING CONTROL DEGRADATION AND NBTI/PBTI TOLERANT DESIGN FOR WRITE-REPLICA CIRCUIT IN NANOSCALE CMOS SRAM
|
Yang, Shyh-Chyi; Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:25Z |
A MICRO-WATT MULTI-PORT REGISTER FILE WITH WIDE OPERATING VOLTAGE RANGE
|
Yang, Shyh-Chyi; Yang, Hao-I; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices
|
Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:19Z |
Impact of Gate-Oxide Breakdown on Power-Gated SRAM
|
Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:05Z |
On-chip DC-DC converter with frequency detector for dynamic voltage scaling technology
|
Yang, Jen-Wei; Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:05Z |
Low power pre-comparison scheme for NOR-type 10T content addressable memory
|
Huang, Po-Tsang; Chang, Wei-Keng; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:05Z |
A low-power reconfigurable mixed-radix FFT/IFFT processor
|
Lai, Chi-Chen; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:24:51Z |
2-l.evel FIFO architecture design for switch fabrics in network-on-chip
|
Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:24:51Z |
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
|
Chao, Tzu-Chiang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:24:49Z |
A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM
|
Hua, Chung-Hsien; Peng, Chi-Wei; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:24:05Z |
Design and Iso-Area V-min Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS
|
Chang, Ming-Hung; Chiu, Yi-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:23:36Z |
Impacts of NBTI and PBTI on Power-Gated SRAM with High-k Metal-Gate Devices
|
Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:23:15Z |
An Adaptive Congestion-Aware Routing Algorithm for Mesh Network-on-Chip Platform
|
Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:23:13Z |
A 2.1-mu W 0.3V-1.0V Wide Locking Range Multiphase DLL Using Self-Estimated SAR Algorithm
|
Chang, Yi-Ming; Chang, Ming-Hung; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:23:12Z |
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation
|
Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Logical Effort Models with Voltage and Temperature Extensions in Super-/Near-/Sub-threshold Regions
|
Chang, Ming-Hung; Hsieh, Chung-Ying; Chen, Mei-Wei; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:21:19Z |
On-Demand Memory Sub-System for Multi-Core SaCs
|
Huang, Po-Tsang; Chang, Yung; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:21:19Z |
An Energy-Efficient 10T SRAM-based FIFO Memory Operating in Near-/Sub-threshold Regions
|
Du, Wei-Hung; Chang, Ming-Hung; Yang, Hao-Yi; Hwang, Wei |
