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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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機構 日期 題名 作者
國立交通大學 2014-12-08T15:25:19Z Impact of Gate-Oxide Breakdown on Power-Gated SRAM Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:25:05Z On-chip DC-DC converter with frequency detector for dynamic voltage scaling technology Yang, Jen-Wei; Huang, Po-Tsang; Hwang, Wei
國立交通大學 2014-12-08T15:25:05Z Low power pre-comparison scheme for NOR-type 10T content addressable memory Huang, Po-Tsang; Chang, Wei-Keng; Hwang, Wei
國立交通大學 2014-12-08T15:25:05Z A low-power reconfigurable mixed-radix FFT/IFFT processor Lai, Chi-Chen; Hwang, Wei
國立交通大學 2014-12-08T15:24:51Z 2-l.evel FIFO architecture design for switch fabrics in network-on-chip Huang, Po-Tsang; Hwang, Wei
國立交通大學 2014-12-08T15:24:51Z A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Chao, Tzu-Chiang; Hwang, Wei
國立交通大學 2014-12-08T15:24:49Z A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM Hua, Chung-Hsien; Peng, Chi-Wei; Hwang, Wei
國立交通大學 2014-12-08T15:24:05Z Design and Iso-Area V-min Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS Chang, Ming-Hung; Chiu, Yi-Te; Hwang, Wei
國立交通大學 2014-12-08T15:23:36Z Impacts of NBTI and PBTI on Power-Gated SRAM with High-k Metal-Gate Devices Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:23:15Z An Adaptive Congestion-Aware Routing Algorithm for Mesh Network-on-Chip Platform Huang, Po-Tsang; Hwang, Wei
國立交通大學 2014-12-08T15:23:13Z A 2.1-mu W 0.3V-1.0V Wide Locking Range Multiphase DLL Using Self-Estimated SAR Algorithm Chang, Yi-Ming; Chang, Ming-Hung; Hwang, Wei
國立交通大學 2014-12-08T15:23:12Z All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation Hsieh, Wei-Chih; Hwang, Wei
國立交通大學 2014-12-08T15:21:45Z Logical Effort Models with Voltage and Temperature Extensions in Super-/Near-/Sub-threshold Regions Chang, Ming-Hung; Hsieh, Chung-Ying; Chen, Mei-Wei; Hwang, Wei
國立交通大學 2014-12-08T15:21:19Z On-Demand Memory Sub-System for Multi-Core SaCs Huang, Po-Tsang; Chang, Yung; Hwang, Wei
國立交通大學 2014-12-08T15:21:19Z An Energy-Efficient 10T SRAM-based FIFO Memory Operating in Near-/Sub-threshold Regions Du, Wei-Hung; Chang, Ming-Hung; Yang, Hao-Yi; Hwang, Wei
國立交通大學 2014-12-08T15:21:19Z A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control Yang, Hao-I; Yang, Shih-Chi; Hsia, Mao-Chih; Lin, Yung-Wei; Lin, Yi-Wei; Chen, Chien-Hen; Chang, Chi-Shin; Lin, Geng-Cing; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang
國立交通大學 2014-12-08T15:20:35Z Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks Huang, Po-Tsang; Hwang, Wei
國立交通大學 2014-12-08T15:20:11Z Impacts of NBTI on SRAM Array with Power Gating Structure Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:16:37Z A 256x128 energy-efficient TCAM with novel low power schemes Huang, Po-Tsang; Chang, Shu-Wei; Liu, Wen-Yen; Hwang, Wei
國立交通大學 2014-12-08T15:16:36Z Power gating technique for embedded pseudo SRAM Cheng, Ching-Yun; Chang, Ming-Hung; Hwang, Wei
國立交通大學 2014-12-08T15:12:41Z Low power and reliable interconnection with self-corrected green coding scheme for network-on-chip Huang, Po-Tsang; Fang, Wei-Li; Wang, Yin-Ling; Hwang, Wei
國立交通大學 2014-12-08T15:11:51Z Design of memory sub-system in H.264/AVC decoder Li, Chih-Hung; Chang, Chang-Hsuan; Peng, Wen-Hsiao; Hwang, Wei; Chiang, Tihao
國立交通大學 2014-12-08T15:10:11Z A flexible two-layer external memory management for H.264/AVC decoder Chang, Chang-Hsuan; Chang, Ming-Hung; Hwang, Wei
國立交通大學 2014-12-08T15:10:09Z A 65nm low power 2T1D embedded DRAM with leakage current reduction Chang, Mu-Tien; Huang, Po-Tsang; Hwang, Wei
國立交通大學 2014-12-08T15:09:30Z Low power on-chip current monitoring medium-grained adaptive voltage control Hsieh, Wei-Chih; Hwang, Wei

顯示項目 176-200 / 202 (共9頁)
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