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"hwang wei"的相關文件
顯示項目 186-195 / 202 (共21頁)
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| 國立交通大學 |
2014-12-08T15:23:13Z |
A 2.1-mu W 0.3V-1.0V Wide Locking Range Multiphase DLL Using Self-Estimated SAR Algorithm
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Chang, Yi-Ming; Chang, Ming-Hung; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:23:12Z |
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation
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Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Logical Effort Models with Voltage and Temperature Extensions in Super-/Near-/Sub-threshold Regions
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Chang, Ming-Hung; Hsieh, Chung-Ying; Chen, Mei-Wei; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:21:19Z |
On-Demand Memory Sub-System for Multi-Core SaCs
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Huang, Po-Tsang; Chang, Yung; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:21:19Z |
An Energy-Efficient 10T SRAM-based FIFO Memory Operating in Near-/Sub-threshold Regions
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Du, Wei-Hung; Chang, Ming-Hung; Yang, Hao-Yi; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:21:19Z |
A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
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Yang, Hao-I; Yang, Shih-Chi; Hsia, Mao-Chih; Lin, Yung-Wei; Lin, Yi-Wei; Chen, Chien-Hen; Chang, Chi-Shin; Lin, Geng-Cing; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:20:35Z |
Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks
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Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:20:11Z |
Impacts of NBTI on SRAM Array with Power Gating Structure
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:16:37Z |
A 256x128 energy-efficient TCAM with novel low power schemes
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Huang, Po-Tsang; Chang, Shu-Wei; Liu, Wen-Yen; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:16:36Z |
Power gating technique for embedded pseudo SRAM
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Cheng, Ching-Yun; Chang, Ming-Hung; Hwang, Wei |
顯示項目 186-195 / 202 (共21頁)
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