|
English
|
正體中文
|
简体中文
|
2875232
|
|
???header.visitor??? :
54172457
???header.onlineuser??? :
900
???header.sponsordeclaration???
|
|
|
|
???tair.name??? >
???browser.page.title.author???
|
"hwang wei"???jsp.browse.items-by-author.description???
Showing items 141-150 of 202 (21 Page(s) Totally) << < 10 11 12 13 14 15 16 17 18 19 > >> View [10|25|50] records per page
| 國立交通大學 |
2014-12-12T01:23:24Z |
高可靠度奈米級靜態隨機存取記憶體設計: 可靠度分析與改善技術
|
楊皓義; Yang, Hao-I; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:23:20Z |
應用於無線影像娛樂系統之以記憶體為重心的晶內互聯網路
|
王湘斐; Wang, Shiang-Fei; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:22:35Z |
適用於二維及矽穿孔三維積體電路之適應性功率管理設計
|
謝維致; Hsieh, Wei-Chih; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-12T01:21:40Z |
應用於多核心系統晶片之節能晶內資料傳輸-以記憶儲存為重心
|
黃柏蒼; Huang, Po-Tsang; 黃威; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:47:26Z |
A Fully-Differential Subthreshold SRAM Cell with Auto-Compensation
|
Chang, Mu-Tien; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:46:20Z |
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
|
Chuang, Li-Pu; Chang, Ming-Hung; Huang, Po-Tsang; Kan, Chih-Hao; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:46:19Z |
"Green" micro-architecture and circuit co-design for ternary content addressable memory
|
Huang, Po-Tsang; Chang, Shu-Wei; Liu, Wen-Yen; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:57Z |
A 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-Calibration
|
Chang, Ming-Hung; Chuang, Li-Pu; Chang, I-Ming; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:56Z |
IN-SITU SELF-AWARE ADAPTIVE POWER CONTROL SYSTEM WITH MULTI-MODE POWER GATING NETWORK
|
Hsieh, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:45:55Z |
A ROBUST ULTRA-LOW POWER ASYNCHRONOUS FIFO MEMORY WITH SELF-ADAPTIVE POWER CONTROL
|
Chang, Mu-Tien; Huang, Po-Tsang; Hwang, Wei |
Showing items 141-150 of 202 (21 Page(s) Totally) << < 10 11 12 13 14 15 16 17 18 19 > >> View [10|25|50] records per page
|