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Showing items 171-180 of 202 (21 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:30:05Z |
Substrate Noise Suppression Technique for Power Integrity of TSV 3D Integration
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Yang, Po-Jen; Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
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Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:40Z |
TIMING CONTROL DEGRADATION AND NBTI/PBTI TOLERANT DESIGN FOR WRITE-REPLICA CIRCUIT IN NANOSCALE CMOS SRAM
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Yang, Shyh-Chyi; Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:25Z |
A MICRO-WATT MULTI-PORT REGISTER FILE WITH WIDE OPERATING VOLTAGE RANGE
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Yang, Shyh-Chyi; Yang, Hao-I; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:19Z |
Impact of Gate-Oxide Breakdown on Power-Gated SRAM
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:05Z |
On-chip DC-DC converter with frequency detector for dynamic voltage scaling technology
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Yang, Jen-Wei; Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:05Z |
Low power pre-comparison scheme for NOR-type 10T content addressable memory
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Huang, Po-Tsang; Chang, Wei-Keng; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:25:05Z |
A low-power reconfigurable mixed-radix FFT/IFFT processor
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Lai, Chi-Chen; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:24:51Z |
2-l.evel FIFO architecture design for switch fabrics in network-on-chip
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Huang, Po-Tsang; Hwang, Wei |
Showing items 171-180 of 202 (21 Page(s) Totally)
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