| 國立交通大學 |
2014-12-16T06:16:05Z |
Clock switching circuit
|
Wu, Jian-Hua; Hwang, Wei |
| 國立交通大學 |
2014-12-16T06:15:57Z |
Pipeline-based reconfigurable mixed-radix FFT processor
|
Lai, Chi-Chen; Hwang, Wei |
| 國立交通大學 |
2014-12-16T06:15:56Z |
BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBY
|
Huang, Po-Tsang; Hwang, Wei; Chang, Shu-Wei |
| 國立交通大學 |
2014-12-16T06:15:56Z |
STORED DON'T-CARE BASED HIERARCHICAL SEARCH-LINE SCHEME
|
CHANG, Shu-Wei; Hwang, Wei; Chang, Ming-Hung; Huang, Po-Tsang |
| 國立交通大學 |
2014-12-16T06:15:49Z |
SELF-AWARE ADAPTIVE POWER CONTROL SYSTEM AND A METHOD FOR DETERMINING THE CIRCUIT STATE
|
HSIEH, Wei-Chih; Hwang, Wei |
| 國立交通大學 |
2014-12-16T06:15:48Z |
Leakage current cut-off device for ternary content addressable memory
|
Huang, Po-Tsang; Liu, Wen-Yen; Hwang, Wei |
| 國立交通大學 |
2014-12-16T06:15:48Z |
Super leakage current cut-off device for ternary content addressable memory
|
Huang, Po-Tsang; Liu, Wen-Yen; Hwang, Wei |
| 國立交通大學 |
2014-12-16T06:15:33Z |
Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus
|
Chang, Mu-Tien; Huang, Po-Tsang; Hwang, Wei |
| 國立交通大學 |
2014-12-16T06:15:25Z |
DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL
|
Chuang Ching-Te; Yang Hao-I; Lin Jihi-Yu; Yang Shyh-Chyi; Tu Ming-Hsien; Hwang Wei; Jou Shyh-Jye; Lee Kun-Ti; Li Hung-Yu |
| 國立交通大學 |
2014-12-16T06:15:23Z |
Charge Pump
|
WU Chun-Yi; HSIEH Wei-Chih; CHANG Ming-Hung; HWANG Wei |
| 國立交通大學 |
2014-12-16T06:15:23Z |
SOLAR POWER MANAGEMENT SYSTEM
|
WU CHUN-YI; HSIEH WEI-CHIH; HWANG WEI |
| 國立交通大學 |
2014-12-16T06:15:18Z |
LOW POWER STATIC RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Hwang Wei; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:15:18Z |
STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Lin Yung-Wei; Lu Chien-Yu; Tu Ming-Hsien; Hwang Wei; Jou Shyh-Jye; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:15:17Z |
DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Yang Hao-I; Lin Yi-Wei; Hwang Wei; Shih Wei-Chiang; Chen Chia-Cheng |
| 國立交通大學 |
2014-12-16T06:15:16Z |
FULLY-ON-CHIP TEMPERATURE, PROCESS, AND VOLTAGE SENSOR SYSTEM
|
CHEN Shi-Wen; CHANG Ming-Hung; HSIEH Wei-Chih; HWANG Wei |
| 國立交通大學 |
2014-12-16T06:15:14Z |
GATE OXIDE BREAKDOWN-WITHSTANDING POWER SWITCH STRUCTURE
|
YANG Hao-I; Chuang Ching-Te; Hwang Wei |
| 國立交通大學 |
2014-12-16T06:15:09Z |
METHOD FOR BUFFERING CLOCK SKEW BY USING A LOGICAL EFFORT
|
Hsieh Chung-Ying; Chang Ming-Hung; Hwang Wei |
| 國立交通大學 |
2014-12-16T06:15:06Z |
STATIC RANDOM ACCESS MEMORY CELL AND METHOD OF OPERATING THE SAME
|
Chiu Yi-Te; Chang Ming-Hung; Yang Hao-I; Hwang Wei |
| 國立交通大學 |
2014-12-16T06:15:04Z |
DUAL-PORT SUBTHRESHOLD SRAM CELL
|
Chiu Yi-Te; Chang Ming-Hung; Yang Hao-I; Hwang Wei |
| 國立交通大學 |
2014-12-16T06:15:01Z |
SYSTEM AND METHOD FOR ALLOCATING CACHE MEMORY
|
CHANG Yung; Huang Po-Tsang; Hwang Wei |
| 國立交通大學 |
2014-12-16T06:15:01Z |
METHOD AND DEVICE FOR DECODING A SCALABLE VIDEO SIGNAL UTILIZING AN INTER-LAYER PREDICTION
|
CHANG YUNG; HUANG PO-TSANG; HWANG WEI; CHEN YU-CHEN; LI GWO-LONG; CHANG TIAN-SHEUAN |
| 國立交通大學 |
2014-12-16T06:14:56Z |
SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor
|
CHUANG Ching-Te; Jou Shyh-Jye; Hwang Wei; Lin Yi-Wei; Tsai Ming-Chien; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di |
| 國立交通大學 |
2014-12-16T06:14:56Z |
Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability
|
Chuang Ching-Te; Jou Shyh-Jye; Hwang Wei; Tsai Ming-Chien; Lin Yi-Wei; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di |
| 國立交通大學 |
2014-12-16T06:14:49Z |
STATIC RANDOM ACCESS MEMORY WITH RIPPLE BIT LINES/SEARCH LINES FOR IMROVING CURRENT LEAKAGE/VARIATION TOLERANCE AND DENSITY/PERFORMANCE
|
CHUANG Ching-Te; YANG Hao-I; LU Chien-Yu; CHEN Chien-Hen; CHANG Chi-Shin; HUANG Po-Tsang; LAI Shu-Lin; HWANG Wei; JOU Shyh-Jye; TU Ming-Hsien |
| 國立交通大學 |
2014-12-16T06:14:46Z |
TEN-TRANSISTOR DUAL-PORT SRAM WITH SHARED BIT-LINE ARCHITECTURE
|
HWANG Wei; WANG Dao-Ping |
