臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

	English \| 正體中文 \| 简体中文 \| Total items :0
	Visitors : 50685980 Online Users : 253 Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library

Scope

Adv. Search

Login

Administrator

臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

About TAIR
	About TAIR

Browse By
	Institution
	Author
	Title
	Date
	Statistics Chart
	Institution Facts
	Trend

News
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

Copyright
	Publisher & Journal Policy
	TAIR Copyright Conference Minutes

Related Links
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"j b kuo"

Return to Browse by Author
Sorting by Title	Sort by Date

Showing items 151-160 of 176 (18 Page(s) Totally)
<< < 9 10 11 12 13 14 15 16 17 18 > >>
View [10|25|50] records per page

Institution	Date	Title	Author
臺大學術典藏	2018-09-10T04:35:18Z	Novel Sub-1V CMOS Domino Dynamic Logic Circuit Using a Direct Bootstrap (DB) Technique for Low-voltage CMOS VLSI	P. C. Chen; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:18Z	A Novel 0.8V BP-DTMOS Content Addressable Memory Cell Circuit Derived from SOI-DTMOS Techniques	E. Shen; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:18Z	Analysis of Gate Misalignment Effect on the Threshold Voltage of Double-Gate (DG) Ultrathin FD SOI NMOS Devices Using a Compact Model Considering Fringing Electric Field Effect	J. B. Kuo; E. C. Sun; M. T. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:06Z	The Fringing Electric Field Effect on the Short-Channel Effect Threshold Voltage of FD SOI NMOS Devices with LDD/Sidewall Oxide Spacer Structure	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:06Z	Fringing-Induced Barrier Lowering (FIBL) Effects of 100nm FD SOI NMOS Devices with High Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer	S. C. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:06Z	Compact Breakdown Model for PD SOI NMOS Devices Considering BJT/MOS Impact Ionization for SPICE Circuits Simulation	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:06Z	High-Temperature Quasi-Saturation Model of High-Voltage DMOS Power Devices	C. L. Yang; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:05Z	Sub-1V CMOS Large Capacitive-Load Driver Circuit Using Direct Bootstrap Technique for Low-Voltage CMOS VLSI	P. C. Chen; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:05Z	A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme	P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:15Z	Novel 0.8V True-Single-Phase-Clocking (TSPC) Latches Using PD-SOI DTMOS Techniques for Low-Voltage CMOS VLSI Circuits	J. B. Kuo; T. Y. Chiang; JAMES-B KUO

Showing items 151-160 of 176 (18 Page(s) Totally)
<< < 9 10 11 12 13 14 15 16 17 18 > >>
View [10|25|50] records per page