臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T03:50:15Z	Low-Voltage SOI CMOS VLSI Devices and Circuits	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell	P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell	P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques	S. C. Liu; J. B. Kuo; Frank Wu; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	Future Trends on SOI CMOS VLSI	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2013-12	Turn-on Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect	D. H. Lung;J. B. Kuo;D. Chen; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2013-12	Turn-on Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect	D. H. Lung;J. B. Kuo;D. Chen; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2012-12	A Closed-form Analytical Transient Response Model for On-Chip Distortionless Interconnect	T. C. Liu;J. B. Kuo;S. D. Zhang; T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO
臺大學術典藏	2012-12	A Closed-form Analytical Transient Response Model for On-Chip Distortionless Interconnect	T. C. Liu;J. B. Kuo;S. D. Zhang; T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO

Showing items 161-170 of 176 (18 Page(s) Totally)
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