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機構	日期	題名	作者
臺大學術典藏	2018-09-10T15:36:25Z	A Continuous Compact Model Incorporating Higher-Order Correction for Junctionless Nanowire Tansistors with Arbitrary Doping Profiles	C Hong;L. Yang;Q. Cheng;T. Han;J. B. Kuo;Y. Chen; C Hong; L. Yang; Q. Cheng; T. Han; J. B. Kuo; Y. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:36:25Z	A Continuous Compact Model Incorporating Higher-Order Correction for Junctionless Nanowire Tansistors with Arbitrary Doping Profiles	C Hong;L. Yang;Q. Cheng;T. Han;J. B. Kuo;Y. Chen; C Hong; L. Yang; Q. Cheng; T. Han; J. B. Kuo; Y. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:36:25Z	A Nonlinear Surface-Field Compact Model for Juinctionless Nanowire MOSFET	C. Hong;L. Yang;Q. Cheng;T. Han;J. B. Kuo;Y. Chen; C. Hong; L. Yang; Q. Cheng; T. Han; J. B. Kuo; Y. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:36:25Z	A Nonlinear Surface-Field Compact Model for Juinctionless Nanowire MOSFET	C. Hong;L. Yang;Q. Cheng;T. Han;J. B. Kuo;Y. Chen; C. Hong; L. Yang; Q. Cheng; T. Han; J. B. Kuo; Y. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:25:58Z	Floating-body-correlated subthreshold behavior of SOI NMOS device considering back-gate-bias effect	S. K. Hu;J. B. Kuo;Y. J. Chen; S. K. Hu; J. B. Kuo; Y. J. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:25:58Z	Floating-body-correlated subthreshold behavior of SOI NMOS device considering back-gate-bias effect	S. K. Hu;J. B. Kuo;Y. J. Chen; S. K. Hu; J. B. Kuo; Y. J. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:25:58Z	Analysis of Subthreshold Behavior of SOI NMOS De ice Considering Back-Gate-Bias-Related Flaoting Body Effect	S. K. Hu;J. B. Kuo; S. K. Hu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:25:58Z	Analysis of Subthreshold Behavior of SOI NMOS De ice Considering Back-Gate-Bias-Related Flaoting Body Effect	S. K. Hu;J. B. Kuo; S. K. Hu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Compact Modeling of 40nm Pd SOI NMOS Devices Considering Floating Body Effect	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Compact Modeling of 40nm Pd SOI NMOS Devices Considering Floating Body Effect	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Parasitic BJT versus DIBL: Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device	D. H. Lung;S. K. Hu;J. B. Kuo;D. Chen; D. H. Lung; S. K. Hu; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Parasitic BJT versus DIBL: Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device	D. H. Lung;S. K. Hu;J. B. Kuo;D. Chen; D. H. Lung; S. K. Hu; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	A Surface-Field-Based Model for Nanowire MOSFETs with Spatial Variations of Doping Profiles	Q. Cheng;C. Y. Hong;J. B. Kuo;Y. J. Chen; Q. Cheng; C. Y. Hong; J. B. Kuo; Y. J. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	A Surface-Field-Based Model for Nanowire MOSFETs with Spatial Variations of Doping Profiles	Q. Cheng;C. Y. Hong;J. B. Kuo;Y. J. Chen; Q. Cheng; C. Y. Hong; J. B. Kuo; Y. J. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Subthreshold Behavior of the SOI NMOS Device Consdiering BJT and DIBL Effects	D. H. Lung;J. B. Kuo; D. H. Lung; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Subthreshold Behavior of the SOI NMOS Device Consdiering BJT and DIBL Effects	D. H. Lung;J. B. Kuo; D. H. Lung; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC	G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC	G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs	JAMES-B KUO; J. B. Kuo; G. Lin; G. Lin;J. B. Kuo
臺大學術典藏	2018-09-10T15:00:17Z	Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs	JAMES-B KUO; J. B. Kuo; G. Lin; G. Lin;J. B. Kuo
臺大學術典藏	2018-09-10T15:00:17Z	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO

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