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機構 日期 題名 作者
臺大學術典藏 2018-09-10T08:46:16Z Modeling the Floating-Body-Effect-Related Transient Behavior of 40nm PD SOI NMOS Device via the SPICE Bipolar/MOS Model S. W. Fang; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:46:16Z A Novel Low-Voltage Silicon-On-Insulator (SOI) CMOS Complementary Pass-Transistor Logic (CPL) Circuit using Asymmetrical Dynamic Threshold Pass-Transistor (ADTPT) Technique J. B. Kuo;B. T. Wang; J. B. Kuo; B. T. Wang; JAMES-B KUO
臺大學術典藏 2018-09-10T08:46:16Z A Novel Low-Voltage Silicon-On-Insulator (SOI) CMOS Complementary Pass-Transistor Logic (CPL) Circuit using Asymmetrical Dynamic Threshold Pass-Transistor (ADTPT) Technique J. B. Kuo;B. T. Wang; J. B. Kuo; B. T. Wang; JAMES-B KUO
臺大學術典藏 2018-09-10T08:46:16Z A Charge-Sharing-Problem-Free 1.5V BiCMOS Dynamic Logic Gate Circuit J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T08:46:16Z A Charge-Sharing-Problem-Free 1.5V BiCMOS Dynamic Logic Gate Circuit J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T08:46:15Z Analysis of Turn-off Transient Behavior of the 40nm PD SOI NMOS Device with the Floating Body Effect C. H. Chen; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Modeling the Floating-Body-Effect-Induced Drain Current Behavior of 40nm PD SOI NMOS Device Via SPICE BJT/MOS Model Approach J. S. Su;J. B. Kuo;D. Chen;C. S. Yeh; J. S. Su; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Modeling the Floating-Body-Effect-Induced Drain Current Behavior of 40nm PD SOI NMOS Device Via SPICE BJT/MOS Model Approach J. S. Su;J. B. Kuo;D. Chen;C. S. Yeh; J. S. Su; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design Optimization of Low-power SOC Applications W.C.H. Lin;J. B. Kuo; W.C.H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design Optimization of Low-power SOC Applications W.C.H. Lin;J. B. Kuo; W.C.H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Modeling the parasitic bipolar device in the 40nm PD SOI NMOS device considering the floating body effect C. H. Chen;J. B. Kuo;D. Chen;C. S. Yeh; C. H. Chen; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Modeling the parasitic bipolar device in the 40nm PD SOI NMOS device considering the floating body effect C. H. Chen;J. B. Kuo;D. Chen;C. S. Yeh; C. H. Chen; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Charge Pumping Behavior of STI-Isolated PD SOI NMOS Device Operating at Low Temp C. F. Yen;J. B. Kuo; C. F. Yen; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:06Z Charge Pumping Behavior of STI-Isolated PD SOI NMOS Device Operating at Low Temp C. F. Yen;J. B. Kuo; C. F. Yen; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:05Z Shallow trench isolation-related narrow channel effect on the kink behaviour of 40 nm PD SOI NMOS device H. J. Hung;J. B. kuo;D. Chen;C. T. Tsai;C. S. Yeh; H. J. Hung; J. B. kuo; D. Chen; C. T. Tsai; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T08:18:05Z Shallow trench isolation-related narrow channel effect on the kink behaviour of 40 nm PD SOI NMOS device H. J. Hung;J. B. kuo;D. Chen;C. T. Tsai;C. S. Yeh; H. J. Hung; J. B. kuo; D. Chen; C. T. Tsai; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:38Z Compact Modelign of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:38Z Compact Modelign of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:38Z Floating-Body-Effect-Related Gate Tunneling Leakage Current Phenomenon of 40nm PD SOI NMOS Device H. J. Hung;J. B. Kuo;C. T. Tsai;D. Chen; H. J. Hung; J. B. Kuo; C. T. Tsai; D. Chen; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:38Z Floating-Body-Effect-Related Gate Tunneling Leakage Current Phenomenon of 40nm PD SOI NMOS Device H. J. Hung;J. B. Kuo;C. T. Tsai;D. Chen; H. J. Hung; J. B. Kuo; C. T. Tsai; D. Chen; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:38Z Low-Voltage CMOS VLSI Circuits J. B. Kuo; J. H. Lou; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Shallow Trench Isolated-Related Narrow Channel Effect on Kink Effect and Breakdown Behavior of 40nm PD SOI NMOS Device J. I. Lu;H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh;C. T. Tsai; J. I. Lu; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Shallow Trench Isolated-Related Narrow Channel Effect on Kink Effect and Breakdown Behavior of 40nm PD SOI NMOS Device J. I. Lu;H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh;C. T. Tsai; J. I. Lu; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Floating-body-effect-related gate tunneling leakage current phenomenon of 40nm PD SOI NMOS device H. J. Hung;J. I. Lu;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. I. Lu; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Floating-body-effect-related gate tunneling leakage current phenomenon of 40nm PD SOI NMOS device H. J. Hung;J. I. Lu;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. I. Lu; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z 0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications W. J. H. Lin;C. Y. Chien;J. B. Kuo; W. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z 0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications W. J. H. Lin;C. Y. Chien;J. B. Kuo; W. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique C. H. Lin;J. B. Kuo; C. H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique C. H. Lin;J. B. Kuo; C. H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Modeling the Floating-Body-Effect-Induced Drain Current Behavior of PD SOI NMOS Device Via SPICE BJT/MOS Model Approach J. S. Su;J. B. Kuo; J. S. Su; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Modeling the Floating-Body-Effect-Induced Drain Current Behavior of PD SOI NMOS Device Via SPICE BJT/MOS Model Approach J. S. Su;J. B. Kuo; J. S. Su; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device Considerign the Floating Body Effect H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:37Z Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device Considerign the Floating Body Effect H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:36Z Temperature-Dependent Kink Effect Model for Partially-Depleted SOI NMOS Devices S. C Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:36Z Bandgap Narrowing J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:36Z Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide C. H. Lin;J. B. Kuo; C. H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:36Z Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide C. H. Lin;J. B. Kuo; C. H. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:36Z Compact MOS/Bipolar Charge-Control Model of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation---SOI-Technology (ST)-SPICE J. B. Kuo; K. W. Su; S. C. Lin; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:36Z A Novel 0.7V Two-Port 6T SRAM Memory Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially Depleted SOI Dynamic-Threshold Technique S. C. Liu; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:36Z Semiconductor R&D in Taiwan J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:35Z A CMOS Semi-Static Latch Circuit without Charge Sharing and Leakage Current Problems P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:35Z A Low-Voltage Semi-Dynamic DCVSPG-Domino Logic Circuit J. H. Lou; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:41:35Z Modeling of Deep-Submicron SOI CMOS VLSI Devices J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:08:19Z Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications R. Chen; R. Liu; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:08:19Z Analysis of STI Mechanical-Stress Induced Effects on 40nm PD SOI NMOS Devices J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:08:19Z Analysis of STI Mechanical-Stress Induced Effects on 40nm PD SOI NMOS Devices J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:08:19Z Transient Behavior of 40nm PD SOI NMOS Device Considering STI-Induced Mechanical Stress Effects J. S. Su;J. B. Kuo; J. S. Su; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T07:08:19Z Transient Behavior of 40nm PD SOI NMOS Device Considering STI-Induced Mechanical Stress Effects J. S. Su;J. B. Kuo; J. S. Su; J. B. Kuo; JAMES-B KUO

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