臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 136-145 of 176 (18 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T06:02:15Z	Fringing Effects of Nanometer SOI CMOS Devices	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T05:26:48Z	Fringing-Induced Narrow-Channel-Effect (FINCE) RElated Capacitance Behavior of Nanometer FD SOI NMOS Devices Using Mesa-Isolation Via 3D Simulation	G. S. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T05:26:48Z	CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects	Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:04Z	Gate Misalignment Effect Related Capacitance Behavior of a 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gate	C. H. Hsu; C. P. Yang; JAMES-B KUO; J. B. Kuo
臺大學術典藏	2018-09-10T04:59:04Z	Low-Voltage SOI CMOS VLSI Devices and Circuits	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI NMOS Devices Considering Fringing Electric Field Effects	E. C. Sun; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	PD SOI-Technology SPICE Models	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	A Low-Voltage CMOS Load Driver with the Adiabatic and Bootstrap Techniques for Low-Power System Applications	J. B. Kuo;H. P. Chen; J. B. Kuo; H. P. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	A Low-Voltage CMOS Load Driver with the Adiabatic and Bootstrap Techniques for Low-Power System Applications	J. B. Kuo;H. P. Chen; J. B. Kuo; H. P. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	Trends on CMOS VLSI	J. B. Kuo; JAMES-B KUO

Showing items 136-145 of 176 (18 Page(s) Totally)
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