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Showing items 141-176 of 176 (4 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T04:59:03Z	A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI NMOS Devices Considering Fringing Electric Field Effects	E. C. Sun; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	PD SOI-Technology SPICE Models	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	A Low-Voltage CMOS Load Driver with the Adiabatic and Bootstrap Techniques for Low-Power System Applications	J. B. Kuo;H. P. Chen; J. B. Kuo; H. P. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	A Low-Voltage CMOS Load Driver with the Adiabatic and Bootstrap Techniques for Low-Power System Applications	J. B. Kuo;H. P. Chen; J. B. Kuo; H. P. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T04:59:03Z	Trends on CMOS VLSI	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:19Z	Compact Modeling of SOI CMOS VLSI Devices	J. .B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:19Z	Asymmetric Gate Misalignment Effect on Subthreshold Characteristics DG SOI NMOS Devices Considering Fringing Electric Field Effect	M. T. Lin; E. C. Sun; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:18Z	Ultra-low-voltage SOI CMOS Inverting Driver Circuit Using Effective Charge Pump Based on Bootstrap Technique	JAMES-B KUO; J. B. Kuo; J. H. T. Chen
臺大學術典藏	2018-09-10T04:35:18Z	Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure	S. C. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:18Z	SOI CMOS VLSI	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:18Z	Novel Sub-1V CMOS Domino Dynamic Logic Circuit Using a Direct Bootstrap (DB) Technique for Low-voltage CMOS VLSI	P. C. Chen; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:18Z	A Novel 0.8V BP-DTMOS Content Addressable Memory Cell Circuit Derived from SOI-DTMOS Techniques	E. Shen; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:35:18Z	Analysis of Gate Misalignment Effect on the Threshold Voltage of Double-Gate (DG) Ultrathin FD SOI NMOS Devices Using a Compact Model Considering Fringing Electric Field Effect	J. B. Kuo; E. C. Sun; M. T. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:06Z	The Fringing Electric Field Effect on the Short-Channel Effect Threshold Voltage of FD SOI NMOS Devices with LDD/Sidewall Oxide Spacer Structure	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:06Z	Fringing-Induced Barrier Lowering (FIBL) Effects of 100nm FD SOI NMOS Devices with High Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer	S. C. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:06Z	Compact Breakdown Model for PD SOI NMOS Devices Considering BJT/MOS Impact Ionization for SPICE Circuits Simulation	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:06Z	High-Temperature Quasi-Saturation Model of High-Voltage DMOS Power Devices	C. L. Yang; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:05Z	Sub-1V CMOS Large Capacitive-Load Driver Circuit Using Direct Bootstrap Technique for Low-Voltage CMOS VLSI	P. C. Chen; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T04:15:05Z	A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme	P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:15Z	Novel 0.8V True-Single-Phase-Clocking (TSPC) Latches Using PD-SOI DTMOS Techniques for Low-Voltage CMOS VLSI Circuits	J. B. Kuo; T. Y. Chiang; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:15Z	Low-Voltage SOI CMOS VLSI Devices and Circuits	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell	P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell	P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques	S. C. Liu; J. B. Kuo; Frank Wu; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model	J. B. Kuo; S. C. Lin; JAMES-B KUO
臺大學術典藏	2018-09-10T03:50:14Z	Future Trends on SOI CMOS VLSI	J. B. Kuo; JAMES-B KUO
臺大學術典藏	2013-12	Turn-on Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect	D. H. Lung;J. B. Kuo;D. Chen; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2013-12	Turn-on Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect	D. H. Lung;J. B. Kuo;D. Chen; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2012-12	A Closed-form Analytical Transient Response Model for On-Chip Distortionless Interconnect	T. C. Liu;J. B. Kuo;S. D. Zhang; T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO
臺大學術典藏	2012-12	A Closed-form Analytical Transient Response Model for On-Chip Distortionless Interconnect	T. C. Liu;J. B. Kuo;S. D. Zhang; T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO
臺大學術典藏	2012-04	Function of the parasitic bipolar transistor in the 40 nm PD SOI NMOS device considering the floating body effect	C. H. Chen;J. B. Kuo;D. Chen;C. S. Yeh; C. H. Chen; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏	2012-04	Function of the parasitic bipolar transistor in the 40 nm PD SOI NMOS device considering the floating body effect	C. H. Chen;J. B. Kuo;D. Chen;C. S. Yeh; C. H. Chen; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏	2001-05	Low-Voltage Content Addressable Memory Cell with a Fast Tag-Compare Capability Using Partially-Depleted SOI CMOS Dynamic-Threshold Techniques	JAMES-B KUO; S. C. Liu; J. B. Kuo
臺大學術典藏	1999-05	A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation	J. H. Lou; J. B. Kuo; JAMES-B KUO
臺大學術典藏	0-01	A High-Speed 1.5V Clocked BiCMOS Latch for BiCMOS Dynamic Pipelined Digital Logic VLSI Systems	J. B. Kuo;J. H. Lou; J. B. Kuo; J. H. Lou; JAMES-B KUO
臺大學術典藏	0-01	A High-Speed 1.5V Clocked BiCMOS Latch for BiCMOS Dynamic Pipelined Digital Logic VLSI Systems	J. B. Kuo;J. H. Lou; J. B. Kuo; J. H. Lou; JAMES-B KUO

Showing items 141-176 of 176 (4 Page(s) Totally)
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